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2N3055 failure (power supply)

J

John Larkin

Since *someone* pointed out that the previous MOSFETs were small packages,
I ran another simulation with honking big devices. STB120NF10 (D2PAK),
IRFP2907 (TO-247), and IRF1405 (TO-220).

Rload Vload I(R1) I(R2) I(R3)
0.2 9.11 15.6A 14.3A 15.7A
0.5 10.17 7.16A 5.52A 7.66A
1.0 10.61 3.88A 2.17A 4.56A
1.5 10.78 2.71A 1.03A 3.45A
2.0 10.87 2.09A 0.48A 2.86A
5.0 11.10 0.72A 587pA 1.51A

Even with such major device differences, the current sharing is not too bad
at high levels where it is critical.

Paul

If you're still assuming 0.1 ohms in each source, the high-current
point results in about 1.5 volts drop in each source resistor, or
about 22 watts dissipated per resistor. Sure, that works if you don't
mind all that heat. But the low-current sharing is correspondingly
terrible.

It's interesting that the TO-247 part (which will have the fattest
leads and source wirebonds by far) comes out worst at all currents. I
certainly wouldn't do a production design based on Spice simulations
like this.

John
 
P

Paul E. Schoen

John Larkin said:
If you're still assuming 0.1 ohms in each source, the high-current
point results in about 1.5 volts drop in each source resistor, or
about 22 watts dissipated per resistor. Sure, that works if you don't
mind all that heat. But the low-current sharing is correspondingly
terrible.

It's interesting that the TO-247 part (which will have the fattest
leads and source wirebonds by far) comes out worst at all currents. I
certainly wouldn't do a production design based on Spice simulations
like this.

I added the calculated Vgs for these devices with the 0.1 ohm source
resistors:

STB120NF10 IRFP2907 IRF1405
D2PAK TO-247 TO-220
Rload Vload I(R1)/Vg1 I(R2)/Vg2 I(R3)/Vg3

0.1 7.82 26.5A/4.53 25.6A/4.62 26.2/4.56
0.2 9.11 15.6A/4.33 14.3A/4.46 15.7A/4.23
0.5 10.17 7.16A/4.11 5.52A/4.28 7.66A/4.06
1.0 10.61 3.88A/4.00 2.17A/4.17 4.56A/3.93
1.5 10.78 2.71A/3.95 1.03A/4.12 3.45A/3.88
2.0 10.87 2.09A/3.92 0.48A/4.08 2.86A/3.84
5.0 11.10 0.72A/3.83 587pA/3.90 1.51A/3.75

These voltages are generally below the typical cutoff voltages on the
device data sheets, so the results might not be accurate at the low current
levels.

These are high current devices, so I used lower values to get more current:

With 0.01 ohm source resistors:

0.03 8.63 96.2A/5.41 104.3A/5.33 87.1A/5.50
0.05 9.32 57.6A/5.10 65.4A/5.03 57.6A/5.10
0.1 9.98 35.1A/4.67 32.0A/4.70 32.7A/4.69
0.2 10.41 19.2A/4.40 13.9A/4.45 19.0A/4.40

With 1 uohm source resistors (essentially zero):

0.03 9.52 103.8A/5.48 127.5A/5.48 85.9A/5.48
0.05 9.91 67.5A/5.09 73.7A/5.09 56.9A/5.09
0.1 10.30 37.4A/4.70 32.4A/4.70 33.2A/4.70
0.2 10.58 20.5A/4.42 12.4A/4.42 20.0A/4.42

So, even without negative feedback current sensing, there is adequate
sharing at levels where it counts, and the largest device does finally take
its proper share of the load. Also, the positive temperature coefficient of
device resistance even above saturation will provide even better sharing as
devices heat up.

The main problem with parallel devices appears to be for higher frequency
and switching parameters, and not steady state DC conditions. There could
be problems with a non-resistive dynamic load where currents change
quickly. That could also be simulated, but I don't think it is necessary
unless there is an actual application where this would be required.

Paul
 
J

John Larkin

I added the calculated Vgs for these devices with the 0.1 ohm source
resistors:

STB120NF10 IRFP2907 IRF1405
D2PAK TO-247 TO-220
Rload Vload I(R1)/Vg1 I(R2)/Vg2 I(R3)/Vg3

0.1 7.82 26.5A/4.53 25.6A/4.62 26.2/4.56
0.2 9.11 15.6A/4.33 14.3A/4.46 15.7A/4.23
0.5 10.17 7.16A/4.11 5.52A/4.28 7.66A/4.06
1.0 10.61 3.88A/4.00 2.17A/4.17 4.56A/3.93
1.5 10.78 2.71A/3.95 1.03A/4.12 3.45A/3.88
2.0 10.87 2.09A/3.92 0.48A/4.08 2.86A/3.84
5.0 11.10 0.72A/3.83 587pA/3.90 1.51A/3.75

These voltages are generally below the typical cutoff voltages on the
device data sheets, so the results might not be accurate at the low current
levels.

These are high current devices, so I used lower values to get more current:

With 0.01 ohm source resistors:

0.03 8.63 96.2A/5.41 104.3A/5.33 87.1A/5.50
0.05 9.32 57.6A/5.10 65.4A/5.03 57.6A/5.10
0.1 9.98 35.1A/4.67 32.0A/4.70 32.7A/4.69
0.2 10.41 19.2A/4.40 13.9A/4.45 19.0A/4.40

With 1 uohm source resistors (essentially zero):

0.03 9.52 103.8A/5.48 127.5A/5.48 85.9A/5.48
0.05 9.91 67.5A/5.09 73.7A/5.09 56.9A/5.09
0.1 10.30 37.4A/4.70 32.4A/4.70 33.2A/4.70
0.2 10.58 20.5A/4.42 12.4A/4.42 20.0A/4.42

So, even without negative feedback current sensing, there is adequate
sharing at levels where it counts, and the largest device does finally take
its proper share of the load. Also, the positive temperature coefficient of
device resistance even above saturation will provide even better sharing as
devices heat up.

The main problem with parallel devices appears to be for higher frequency
and switching parameters, and not steady state DC conditions. There could
be problems with a non-resistive dynamic load where currents change
quickly. That could also be simulated, but I don't think it is necessary
unless there is an actual application where this would be required.

Paul

Sorry, I just don't believe these numbers. Spice doesn't include
real-life device-device variations. Transfer curves can be all over
the place, even for parts out of the same tube.

I have used multiple mosfets in parallel in switching apps. That works
fine.

John
 
P

Paul E. Schoen

John Larkin said:
Sorry, I just don't believe these numbers. Spice doesn't include
real-life device-device variations. Transfer curves can be all over
the place, even for parts out of the same tube.

I have used multiple mosfets in parallel in switching apps. That works
fine.

John

I guess someone will need to do actual experimentation to see what happens
in real life. I have not found very much information on device variations,
particularly for gain (transconductance) and gate threshold, which are
probably critical for this application. It would probably be a valuable
exercise to do this. I was very surprised at the current sharing without
source resistors. I would think that the "knee" of the Vgs to I curve is a
useful point. I would think it would vary no more that about 0.2 volts from
the nominal 4.5 volts, especially among similar devices. The source
resistors should take care of that much variation without too much power,
and for linear applications one might as well dissipate some of the power
in resistors rather than the MOSFET. Switching applications are a much
different animal, where efficiency is paramount, and transients are
critical.

An interesting discussion. There is some good information at:
http://www.answers.com/topic/mosfet

Paul
 
P

Phil Allison

"Paul E. Schoen Fucking MORON from HELL "


For more technical analysis of MOSFETs in parallel, read this from IR:

http://www.irf.com/technical-info/appnotes/para.pdf

From what I gather after a quick scan, worst case current imbalances of
about 40% may be expected for devices without additional circuitry such as
source resistors.


** Totally IRRELEVANT article.

The author only considers switching operation - not LINEAR operation.

**** Off - YOU BLOODY IMBECILE !!






......... Phil
 
M

Michael A. Terrell

Jamie said:
Donations any one? :)


I'll donate some laxatives so the shit goes out the other end.


--
Service to my country? Been there, Done that, and I've got my DD214 to
prove it.
Member of DAV #85.

Michael A. Terrell
Central Florida
 
T

Tony Williams

Paul E. Schoen said:
So, even without negative feedback current sensing, there is
adequate sharing at levels where it counts, and the largest
device does finally take its proper share of the load. Also, the
positive temperature coefficient of device resistance even above
saturation will provide even better sharing as devices heat up.

I had a serious rant here a few years ago about the
way in which manufacturers of VMOS devices perpetuated
the myth that "MOSFETs allow easy paralleling".

In fact nothing could be further from the truth.

For the VMOS, at fixed Vgs, dId/dT is positive. This
means that if any one MOSFET in a bank runs slightly
warmer it will take more current, getting hotter, so
taking more current..... and so on. Thermal runaway.

Look at Fig.3 of the IRF1405. At Vgs= 4.5V, Id is
4.2A at Tj=25C, rising to 28A at 175C. That's roughly
+0.15A/C. For the IRF1405 dI/dT does not approach
zero (and go negative) until Id is about 180A.

Hitachi realised this problem 20-odd years ago and
they produced power MOSFETs where dI/dT went negative
at only about 100mA. ISTR they were called lateral
or long channel MOSFETs, an entirely different process
to the VMOS and it's derivatives. The negative dI/dT
did allow easy paralleling and those Hitachi MOSFETs
were widely used in successful high power audio amps.
 
Michael said:
I'll donate some laxatives so the shit goes out the other end.


--
Service to my country? Been there, Done that, and I've got my DD214 to
prove it.
Member of DAV #85.

Michael A. Terrell
Central Florida

I think there is so much it would still have to come out both ends.
 
P

Phil Allison

<[email protected]>



** The above pile of slime is another congenital, ASD FUCKED POMMY **** .

The UK is just crawling with the vile pukes.

Aussie just hate them to death.

Yanks completely despise them.

Other poms just quietly loathe them.


YOU can use you Killfile to eliminate them anytime.






....... Phil
 
Phil said:
<[email protected]>



** The above pile of slime is another congenital, ASD FUCKED POMMY **** .

The UK is just crawling with the vile pukes.

Aussie just hate them to death.

Yanks completely despise them.

Other poms just quietly loathe them.


YOU can use you Killfile to eliminate them anytime.






...... Phil

Repeating yourself again, no imagination. Well no brain so thats to be
expected.
 
M

Mike Monett

[...]
I had a serious rant here a few years ago about the way in which
manufacturers of VMOS devices perpetuated the myth that "MOSFETs
allow easy paralleling".
In fact nothing could be further from the truth.
For the VMOS, at fixed Vgs, dId/dT is positive. This means that if
any one MOSFET in a bank runs slightly warmer it will take more
current, getting hotter, so taking more current. And so on.
Thermal runaway.
Look at Fig.3 of the IRF1405. At Vgs= 4.5V, Id is 4.2A at Tj=25C,
rising to 28A at 175C. That's roughly +0.15A/C. For the IRF1405
dI/dT does not approach zero (and go negative) until Id is about
180A.
Hitachi realised this problem 20-odd years ago and they produced
power MOSFETs where dI/dT went negative at only about 100mA. ISTR
they were called lateral or long channel MOSFETs, an entirely
different process to the VMOS and it's derivatives. The negative
dI/dT did allow easy paralleling and those Hitachi MOSFETs were
widely used in successful high power audio amps.

Good info. Thanks, Tony.

What about the current example using source resistors? These provide
negative feedback, so Vgs is no longer fixed. How do we calculate
the minimum value needed to prevent runaway?

Also, source resistors dissipate some heat, which reduces the amount
dissipated in the MOSFET. So in linear applications such as the
current topic, the source resistor can be useful.

Regards,

Mike Monett

Antiviral, Antibacterial Silver Solution:
http://silversol.freewebpage.org/index.htm
SPICE Analysis of Crystal Oscillators:
http://silversol.freewebpage.org/spice/xtal/clapp.htm
Noise-Rejecting Wideband Sampler:
http://www3.sympatico.ca/add.automation/sampler/intro.htm
 
J

John Larkin

[...]
I had a serious rant here a few years ago about the way in which
manufacturers of VMOS devices perpetuated the myth that "MOSFETs
allow easy paralleling".
In fact nothing could be further from the truth.
For the VMOS, at fixed Vgs, dId/dT is positive. This means that if
any one MOSFET in a bank runs slightly warmer it will take more
current, getting hotter, so taking more current. And so on.
Thermal runaway.
Look at Fig.3 of the IRF1405. At Vgs= 4.5V, Id is 4.2A at Tj=25C,
rising to 28A at 175C. That's roughly +0.15A/C. For the IRF1405
dI/dT does not approach zero (and go negative) until Id is about
180A.
Hitachi realised this problem 20-odd years ago and they produced
power MOSFETs where dI/dT went negative at only about 100mA. ISTR
they were called lateral or long channel MOSFETs, an entirely
different process to the VMOS and it's derivatives. The negative
dI/dT did allow easy paralleling and those Hitachi MOSFETs were
widely used in successful high power audio amps.

Good info. Thanks, Tony.

What about the current example using source resistors? These provide
negative feedback, so Vgs is no longer fixed. How do we calculate
the minimum value needed to prevent runaway?

A positive drain-current tc doesn't guarantee runaway. If the "loop
gain" is less than 1, it won't run away. The math depends on the Id/t
slope, heat sinking, mutual heat sinking, stuff like that. Actually,
true thermal runaway in paralleled mosfets is rare, almost impossible.
Also, source resistors dissipate some heat, which reduces the amount
dissipated in the MOSFET. So in linear applications such as the
current topic, the source resistor can be useful.

In that it reduces power supply headroom and efficiency at peak
output, all it can do is make heat and hurt. In a lot of situations,
there is no value of source resistor that gives decent idle-current
sharing but doesn't introduce huge peak-output losses. The old
nonlinear resistor trick (ie, parallel the emitter resistor with a
diode) often won't work for fets.

John
 
M

Mike Monett

A positive drain-current tc doesn't guarantee runaway. If the
"loop gain" is less than 1, it won't run away. The math depends on
the Id/t slope, heat sinking, mutual heat sinking, stuff like
that.

That's what I hoped Tony might explain.
Actually, true thermal runaway in paralleled mosfets is rare,
almost impossible.

Tony was talking about a single MOSFET with fixed Vgs. His
explanation made good sense.

For paralled MOSFETS, aren't you referring to the fully-saturated
condition where the Rds has a positive temperature coefficient? I
don't think that is the case in this thread.
In that it reduces power supply headroom and efficiency at peak
output, all it can do is make heat and hurt.

How much headroom is lost? What is the minimum value required? If
it's only 0.1V to 1V, it may be a very good tradeoff due to the
simplicity. If it's greater, there may be some other tradeoffs to
consider.

I'm looking for the equations and design procedures to evaluate
these tradeoffs.
In a lot of situations, there is no value of source resistor that
gives decent idle-current sharing but doesn't introduce huge
peak-output losses.

Isn't that a good thing? The power dissipated at idle should be
quite low. Why not have one device carry most of the load? That
should improve linearity and slew rate. Let the other devices come
on line as the load current increases. If they turn on smoothly, it
should add little distortion.
The old nonlinear resistor trick (ie, parallel the emitter
resistor with a diode) often won't work for fets.

Again, where are the equations? What makes it work in some cases and
fail in others?

This could turn into a very useful thread if we could pin down some
numbers:)

Regards,

Mike Monett

Antiviral, Antibacterial Silver Solution:
http://silversol.freewebpage.org/index.htm
SPICE Analysis of Crystal Oscillators:
http://silversol.freewebpage.org/spice/xtal/clapp.htm
Noise-Rejecting Wideband Sampler:
http://www3.sympatico.ca/add.automation/sampler/intro.htm
 
D

Don Bowey

<[email protected]>



** The above pile of slime is another congenital, ASD FUCKED POMMY **** .

The UK is just crawling with the vile pukes.

Aussie just hate them to death.

Yanks completely despise them.

Other poms just quietly loathe them.


YOU can use you Killfile to eliminate them anytime.






...... Phil

Phil,

I'm not up-to-date on insults. What does pommy mean?

Tnx

Don
 
P

Paul E. Schoen

John Larkin said:
[...]
I had a serious rant here a few years ago about the way in which
manufacturers of VMOS devices perpetuated the myth that "MOSFETs
allow easy paralleling".
In fact nothing could be further from the truth.
For the VMOS, at fixed Vgs, dId/dT is positive. This means that if
any one MOSFET in a bank runs slightly warmer it will take more
current, getting hotter, so taking more current. And so on.
Thermal runaway.
Look at Fig.3 of the IRF1405. At Vgs= 4.5V, Id is 4.2A at Tj=25C,
rising to 28A at 175C. That's roughly +0.15A/C. For the IRF1405
dI/dT does not approach zero (and go negative) until Id is about
180A.
Hitachi realised this problem 20-odd years ago and they produced
power MOSFETs where dI/dT went negative at only about 100mA. ISTR
they were called lateral or long channel MOSFETs, an entirely
different process to the VMOS and it's derivatives. The negative
dI/dT did allow easy paralleling and those Hitachi MOSFETs were
widely used in successful high power audio amps.

Good info. Thanks, Tony.

What about the current example using source resistors? These provide
negative feedback, so Vgs is no longer fixed. How do we calculate
the minimum value needed to prevent runaway?

A positive drain-current tc doesn't guarantee runaway. If the "loop
gain" is less than 1, it won't run away. The math depends on the Id/t
slope, heat sinking, mutual heat sinking, stuff like that. Actually,
true thermal runaway in paralleled mosfets is rare, almost impossible.
The same datasheet shows threshold voltage as a function of temperature,
but at a drain current of only 250 uA. I think this is a worst case
scenario. So the change in threshold voltage is 3.3 to 2.7 from 25C to
100C. A 0.1 ohm source resistor will drop 0.4 volts at 4 amps (per the OT
application), so it should ensure reasonable current sharing. Device
temperature difference should not exceed 25C on a good heatsink, so
threshold should only change about 0.2 volts, or 2 amps with the existing
resistors.

Actually a lower current rated MOSFET would probably work better. The
IRF2903Z (75A,30V) shows threshold change from 4.0 to 3.6 volts from 25 to
100C, with drain current of 1 amp, and 3.4 to 2.7 at 1 mA.

The FQB30N06 (30A,60V) shows a current increase from 5A to 9A at fixed gate
voltage of about 4.8V from 25 to 175C, and no change at currents of 25A
with 6.2V Vgs, and negative change above that. Current varies with gate
voltage from 4.5A at 5.0Vgs to 11A at 5.5Vgs.
In that it reduces power supply headroom and efficiency at peak
output, all it can do is make heat and hurt. In a lot of situations,
there is no value of source resistor that gives decent idle-current
sharing but doesn't introduce huge peak-output losses. The old
nonlinear resistor trick (ie, parallel the emitter resistor with a
diode) often won't work for fets.

Given the 22 VDC input voltage (probably about 16 V at full load), and 20
amp 14 volt maximum output, efficiency is not really a factor. The
resistors provide current limiting of about 40 amps if any one of the
devices should short out, if the load is a battery. Also the resistors can
run hotter, and are less expensive than the semiconductor devices. You lose
only about 0.4 V of headroom. And current sharing at idle levels does not
really matter.

Looking at the specs for the bipolar 2N3055, the Vbe changes sharply as a
function of collector current at moderate levels. It is 0.7V at 0.5A, 0.8V
at 2A, 1.0V at 5A, and 1.5V at 10A. This shows that the 0.1 ohm resistors
are more than adequate to ensure safe current sharing at the rated output
of 20A. Much below that it is not so critical. There does appear to be a
need for current limiting or fusing to protect against severe overloads and
short circuits, however.

Another severe limitation with the 2N3055 is the sharp drop of hfe at high
currents. It takes about 1 ampere to drive the output to 10 amps, and 100
mA to drive it to the rated 4 amps per device. Thus you need a solid 2-15
volt 500 mA base drive circuit to get decent output regulation. For the
MOSFETs, you can use a simple voltage divider or pot.

Paul
 
M

martin griffith

Phil,

I'm not up-to-date on insults. What does pommy mean?

Tnx

Don
from a wiki
One theory is that, as the majority of early immigrants to Australia
were British, it is rhyming slang for "immigrant" from a contraction
of the word "pomegranate", or possibly more directly related to the
appearance of the fruit, as it bears a more than passing resemblance
to the typical pale complexioned Briton's skin after his or her first
few days living under the hot Australian sun.


martin
 
J

John Larkin

"Paul E. Schoen = CRIMINAL FUCKWIT "






** How completely hysterical !!!!!!!

All 3 mosfets are in SO-8 pack & have power ratings of 2.5 watts max !!

Isn't that what "sharing" is really about, being willing to die for
your fellow FET?

John
 
P

Paul E. Schoen

John Larkin said:
Isn't that what "sharing" is really about, being willing to die for
your fellow FET?

John

Luckily I ran the simulations for only 10 mSec. Otherwise I might have
burned up my computer. I did find burned spots on my CRT where the MOSFETs
were!

Happy Gnu year,

Paul
 
P

Phil Allison

"Paul E. Schoen Fucking MORON from HELL "



Your totally ASININE simulator is **** NOT **** modelling the production
differences that are **specified ** to EXIST with real MOSFET devices.

Read the flaming spec sheet you BLOODY IMBECILE !!!!!!

The *gate threshold* voltage is speced to range from * 2 to 4 volts
* - for all 3 device types.

With transconductance values from 70 to 130 amps per volt - that means
that parallel connected, unmatched devices
operating in linear mode have NO CHANCE of sharing load current.

A 1 volt gate threshold voltage differential equates to circa 100 amp drain
current error !!!!

http://www.st.com/stonline/products/literature/ds/9522.pdf

See specs on page 4 and figure 4 on page 6.

Draw two extra curves, spaced one volt each side of the curve shown - that
is the region where all real devices fall.


Paul Schoen = a COMPLETE FUCKING ASS !!!!


**** Off - Bloody Imbecile !!!!!!





........ Phil
 
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