Clean square waves using a 555 timer?

[dorke]

I agree with your interpretation.
Regarding the current drawn from pin 3 :
at point A the current is at it's Max and at point B at it's Min.
The higher the current drawn the lower the voltage drop at the output of the 555.
The result is you have a ramping exponential-like output level instead of a "flat plateau one".



Illumination?
Not really, but the above is why you shouldn't use the output signal in a timing circuit of the 555
like in this "non-working" circuit !!!
Instead of charging the capacitor from a "regulated voltage source" you are practically charging it with an un-regulated one,and a timing error will occur.


You can do a few more tests:
1. Add R1=100k to the load(from the junction of the R-C to VCC (like in the original "non-working "circuit)
2. Use an R-C load with R=33K and a corresponding lower C.
3. Use only the 1k resistor as load.

 

[CDRIVE]

This is now a moot point but I doubt that Adam meant for his suggestion to be performed with the circuit powered. Even if he did it's highly unlikely to damage the scope's cal output because the cal's output impedance will be far lower than the value of R2. Thus the cal output will never let the voltage swing to the Vcc or produce excessive current. That said and if he meant powered, I don't blame you for not wanting to take the chance. I'd be hesitant too.

RE Dorks RC test on the output pin:
Your scope results tell me that if the Vcc is stable then that leaves only one possible conclusion. That would be that your 555 isn't delivering the sourcing capabilities that should be expected. I mean 8V/1KΩ= only 8mA! Have you hung a 100Ω load on the output and scoped it? 100Ω should produce 80mA (Vo=8V) of source current, which is still well below the 555's limit.

Chris

 

[Arouse1973]

This is now a moot point but I doubt that Adam meant for his suggestion to be performed with the circuit powered. Even if he did it's highly unlikely to damage the scope's cal output because the cal's output impedance will be far lower than the value of R2. Thus the cal output will never let the voltage swing to the Vcc or produce excessive current. That said and if he meant powered, I don't blame you for not wanting to take the chance. I'd be hesitant too.

RE Dorks RC test on the output pin:
Your scope results tell me that if the Vcc is stable then that leaves only one possible conclusion. That would be that your 555 isn't delivering the sourcing capabilities that should be expected. I mean 8V/1KΩ= only 8mA! Have you hung a 100Ω load on the output and scoped it? 100Ω should produce 80mA (Vo=8V) of source current, which is still well below the 555's limit.

Chris

Yes correct Chris. I just wanted to see what effect the bread board had, I should have said no power. And correct again the calibration output will not have been damaged by this action.
Adam

 

[dorke]

This is now a moot point but I doubt that Adam meant for his suggestion to be performed with the circuit powered. Even if he did it's highly unlikely to damage the scope's cal output because the cal's output impedance will be far lower than the value of R2. Thus the cal output will never let the voltage swing to the Vcc or produce excessive current. That said and if he meant powered, I don't blame you for not wanting to take the chance. I'd be hesitant too.

RE Dorks RC test on the output pin:
Your scope results tell me that if the Vcc is stable then that leaves only one possible conclusion. That would be that your 555 isn't delivering the sourcing capabilities that should be expected. I mean 8V/1KΩ= only 8mA! Have you hung a 100Ω load on the output and scoped it? 100Ω should produce 80mA (Vo=8V) of source current, which is still well below the 555's limit.

Chris

Chris,
The behavior of the output is due to the fact that the load isn't purely resistive,
rather it is a series combination of a largely capacitive one and a resistor.

Test 3 in post #61 should show that the IC has no problem of driving it by itself (i.e a "plateau" output).

 

[CDRIVE]

Chris,
The behavior of the output is due to the fact that the load isn't purely resistive,
rather it is a series combination of a largely capacitive one and a resistor.

Test 3 in post #61 should show that the IC has no problem of driving it by itself (i.e a "plateau" output).

Dork, I realize that but it doesn't matter if that cap was the size of a 50 Gal drum. It still has a 1KΩ in series with it; which will limit the peak current to 8mA.

Chris

 

[dorke]

Chris,
True the 1K limits the current as you say.
But the slopping behavior is entirely due to the series cap.

A voltage drop of 1V(and more )from VCC is normal for the 555,even at relatively low output current of a few mA.
The reason being the output of the 555 isn't rail-to-rail (it is so only for the low output state but not for the high one).
Thus the "difference" between 0 to 8ma is so noticeable .

 

[hevans1944]

So, can we go back to a "standard" astable 555 circuit running at twice the desired frequency and add a Schmitt trigger inverter followed by a D-flop to get half the 555 frequency with a guaranteed 50% duty cycle? All this stuff is now available in single-function itsy bitsy teeny weeny surface-mount components, so you could mount the two parts on a carrier PCB glued to the top of the through-hole mounted 555. Maybe even wire up a handful as spare parts.

 

[dorke]

So, can we go back to a "standard" astable 555 circuit running at twice the desired frequency and add a Schmitt trigger inverter followed by a D-flop to get half the 555 frequency with a guaranteed 50% duty cycle? All this stuff is now available in single-function itsy bitsy teeny weeny surface-mount components, so you could mount the two parts on a carrier PCB glued to the top of the through-hole mounted 555. Maybe even wire up a handful as spare parts.

We should use the circuit with the diode not the "non-working " very problematic circuit.
As I said it isn't a good idea to use the output of the 555 for "auto-timing" purposes,like it is done here.

About your suggestion ,
we could ,up to a point.
As they say "there are many ways to skin a cat"
but that could not be done in all cases:

e.g.
Lets assume you need to create a 100Khz 50% duty-cycle square wave with the 555.
you could theoretically run it at 2x that=200Khz...
oops, can't be done ,it can only be run up-to 100Khz

The 100Khz number is just for illustration (read as the top upper limit of the 555).

 

[Xeno Xenox]

@hevans1944 @dorke:

What I've learned from all of this is that, while the 555 is a versatile chip, it's also very temperamental.

Theory and simulation seem to do a poor job of predicting the real world outcome of 555 circuits, so it's best to build them out and tweak them until you get the effect you want.

 

[dorke]

@hevans1944 @dorke:

What I've learned from all of this is that, while the 555 is a versatile chip, it's also very temperamental.

Theory and simulation seem to do a poor job of predicting the real world outcome of 555 circuits, so it's best to build them out and tweak them until you get the effect you want.

Could you please post the results of the 3 simple test in #61

 

[hevans1944]

If you are limited to using the 555 as your oscillator... well the upper frequency limit is now up to one megahertz. See this Intersil datasheet. It's still a crap shoot what the output waveform will look like. There are "better" oscillator circuits but none quite so versatile as the 555 if you understand the limitations and idiosyncrasies of the device, which no doubt vary from manufacturer to manufacturer as well as between bipolar and CMOS versions.

@Xeno Xenox's original concern was the overshoot after the low-to-high output transition. Where does that come from? Is it possible to eliminate it? Why does the overshoot require a few hundred nanoseconds to drop back to about one volt less than Vcc, the normal output high-state condition? We probably cannot answer these questions without an intimate knowledge of the internal circuitry of the 555, but I suspect it is related to an internal semiconductor capacitance charging up through perhaps the parasitic inductance of the internal lead connections. Generally not a problem with logic applications.

Are we done here?

 

[dorke]

O.K Let's take this to a higher level of understanding:
going into the "guts" of the 555 output stage and it's output characteristics.
I'm going to do it on the intuitive level using equations as little as possible.

First let us start with an NPN transistor in saturation.
In saturation both the B-E and B-C junctions are forward biased.
In terms of currents, saturation means that the ratio IC=beta*IB doesn't hold anymore we instead have IC<beta*IB
The saturation voltages are approximately as follows:
"sat "stands for saturation :
VBEsat=0.8V ,VCEsat=0.2v and VBCsat=0.6V

Now let's have a look at the internals of the 555(equivalent circuit),this is taken from a 70's Signetics datasheet


Looking at the output structure we can identify an NPN "Totem-pole" Q22 and Q24.
In order for the output to be at the "low state" Q24 should be on and Q22-off.
In order for the output to be at the "high state" Q22 should be on and Q24-off.

Looking at Q24,
It has no problem to be in the saturation state (for relatively low output sink current).
VB can be at 0.8V and thus both junctions can be forward biased(voltages noted on the pic).

The low output can be VCEsat=0.2v above the Gnd pin.
We say that the output "can swing to the rail"

Looking at Q22,
It can not be in saturation!
Since the collector is tied at VCC which is the highest voltage in the IC thus VB can't be higher than VC and the B-C junction is reversed biased (ever!) ,Q22 is in the active region.
Looking further at Q21 which drives Q22 ,
we can see that the output(emitter of Q22) needs to be about 2 VBEs drops(that of Q22 and of Q21) below the base of Q21 .
That means it would be at least 1.2V volts below VCC(even at very low output source current).
We say that the output "can not swing to the rail"

A side note:
There is a way to "correct" that by using a PNP for Q22 (and changing it's drive as well).

Finally let's look how this comes together in the 555 output graph.
looking at the 25 Celsius graph only and VCC=15V.

at 1mA : low output =0.025V above GND while the high output is about 1.3V below VCC
at 10mA : low output =0.1V above GND while the high output is about 1.4V below VCC
at 100mA : low output =2.0V above GND while the high output is about 1.7V below VCC





Hope you guys find this helpful.

 

[hevans1944]

Thank you, @dorke, that explains the steady-state performance very well. But in order for the output to, briefly, spike to Vcc and then fall back requires an inductive reactive component to temporarily store the requisite energy.

My guess is this parasitic inductance lies somewhere between the Vcc supply on pin 8 and the bonding wires inside the package, assuming Vcc is adequately bypassed from pin 8 to pin 1 (GND) outside the package and that, during the low-to-high transition, both Q24 and Q22/Q21 are briefly simultaneously conducting to allow that inductance to "charge" with current. That second conjecture, that both output transistors are conducting simultaneously during the transition, appears to be justified by the slight downward blip seen on Vcc about the time of the low-to-high transition.

It would be interesting to model the output stage from Q20 through Q24 in LTSpice and stick some inductance in the Vcc supply to the collectors of Q22/Q21 to observe the effect on the output. This looks like a good "training exercise" for @chopnhack! Of course I have no idea what the transistor parameters for such a model would be...

 

[dorke]

Thank you, @dorke, that explains the steady-state performance very well. But in order for the output to, briefly, spike to Vcc and then fall back requires an inductive reactive component to temporarily store the requisite energy.

My guess is this parasitic inductance lies somewhere between the Vcc supply on pin 8 and the bonding wires inside the package, assuming Vcc is adequately bypassed from pin 8 to pin 1 (GND) outside the package and that, during the low-to-high transition, both Q24 and Q22/Q21 are briefly simultaneously conducting to allow that inductance to "charge" with current. That second conjecture, that both output transistors are conducting simultaneously during the transition, appears to be justified by the slight downward blip seen on Vcc about the time of the low-to-high transition.

It would be interesting to model the output stage from Q20 through Q24 in LTSpice and stick some inductance in the Vcc supply to the collectors of Q22/Q21 to observe the effect on the output. This looks like a good "training exercise" for @chopnhack! Of course I have no idea what the transistor parameters for such a model would be...

1. We know for a fact that the 555 isn't properly decoupled here( post #49 item3).

2. Yes,
the 555 "Totem-pole" is known to bridge the vcc line to GND and produce a large switching current spike.
This point is actually one of the improvements made in the CMOS versions (lower PS switching current).

3. The use of a breadboard isn't making thing better,the build should be a "dead-bug style" or on vero-board.

 

[chopnhack]

It would be interesting to model the output stage from Q20 through Q24 in LTSpice and stick some inductance in the Vcc supply to the collectors of Q22/Q21 to observe the effect on the output. This looks like a good "training exercise" for @chopnhack! Of course I have no idea what the transistor parameters for such a model would be...

LTSpice would be fun for that section, but I don't think it can be simply pulled apart from the rest of the circuit.

Looks like when active, Q20 drives the circuits low and activates the discharge transistor, Q14. It also looks like it supplies the collector of Q25. I assume, when the reset pin is energized with positive voltage, the base has sufficient current to pull the gate high and we have voltage between and current flows to the diode in the center of the page.

I doubt I can add much to the thread, so I will leave you with this link that I found invaluable when looking at the 555 for a circuit: http://www.doctronics.co.uk/555.htm

 

[hevans1944]

I doubt I can add much to the thread, so I will leave you with this link that I found invaluable when looking at the 555 for a circuit: http://www.doctronics.co.uk/555.htm

Thank you. Looks like an excellent resource for the hobbyist.

 

[Xeno Xenox]

@dorke, @hevans1944, et al.

I sincerely appreciate that you are now also interested in finding the theoretical cause of the 555's behavior.

Considering a dead-bug build, I don't have any solid copper PCB board lying around. Would it suffice to solder the circuit onto a prototype board with single pin copper pads using short jumper wires?

At this stage, do you still feel the 10uF tantalum capacitor is a "must have" or can I use a short-lead black canister electrolytic that I have on hand?

 

[Xeno Xenox]

@dorke, @hevans1944, et al.

I sincerely appreciate that you are now also interested in finding the theoretical cause of the 555's behavior.

Considering a dead-bug build, I don't have any solid copper PCB board lying around. Would it suffice to solder the circuit onto a prototype board with single pin copper pads using short jumper wires?

At this stage, do you still feel the 10uF tantalum capacitor is a "must have" or can I use a short-lead black canister electrolytic that I have on hand?

Here's the board I'm thinking of using:

 

[dorke]

Yes ,that would do fine.

Decouple the IC with a tantalum(doesn't have to be 10uF,2.2uF and higher should be fine) and a 0.1uF ceramic and use shortest leads possible.

If you can ,please do the 3 tests in #61 ,on the breadboard.
The results may be interesting.

 

[Xeno Xenox]

Yes ,that would do fine.

Decouple the IC with a tantalum(doesn't have to be 10uF,2.2uF and higher should be fine) and a 0.1uF ceramic and use shortest leads possible.

If you can ,please do the 3 tests in #61 ,on the breadboard.
The results may be interesting.

@dorke:

I purchased 10 tantalum 10uF caps through Amazon for $13.37. They'll arrive Thursday. Do you know of a less expensive source?

When I get some time, I'll try your three tests.

Out of curiosity, is no one else able to build this circuit?