A means of closing a JFET switch with a postive voltage?

[AFex54]

I need to close the JFET in my sample and hold circuit with a postive voltage,
the reason being the sampling must be triggered by a keypress of my CV keyboard, so this mean using the 9V gate signal from the keyboard.
I made a schematic of an idea for this but im fairly sure it wont work,
however it does provide a good visual explantion of what im trying to do,
this will definitely hold the JFET open but I doubt connecting the gate to ground with the 3906 will close it.
there also would be resistors before the transistor base and gate, I just didnt bother adding them in.
:

 

[(*steve*)]

all that circuit will do is short the battery through the transistor when the switch is closed.

do you have a switch off a logic level?

if it is a logic level, do the circuits share a common ground?

 

[Alec_t]

You need to make the gate negative with respect to the source to turn the FET off.

 

[AFex54]

Hmm I was thinking about this and Im wondering do I actually need a switch in my circuit?
I will post in earlier thread of mine in regard to the sample and hold circuit

so because the only time there is an input into the sample and hold circuit is during a sample the only function of the JFET in my case is to act as a diode to hold in the voltage after a sample,
,

 

[CDRIVE]

the only function of the JFET in my case is to act as a diode to hold in the voltage after a sample,
,

I see you're still struggling to keep a negative source out of your project. That 9V battery limitation has been a royal pita. That said I don't understand this statement. You need to elaborate so we can determine whether you should be using a JFET at all. They're not exactly known for being a good switching device.

Chris

 

[AFex54]

I see you're still struggling to keep a negative source out of your project. That 9V battery limitation has been a royal pita. That said I don't understand this statement. You need to elaborate so we can determine whether you should be using a JFET at all. They're not exactly known for being a good switching device.

Chris

my thought was that instead of adding an electronic switch I could take advantage of the mechanical switch in the circuit.

original plan :
as you can see the only time the JFET would be closed is during a sample (but thats only if the JFET could be closed with positive voltage WHICH IT CANT ),

Diode idea:
its now becomes just a hold circuit.
the offset voltage and bias current are miniscule thanks to to LM6144,
If they still pose a problem I was thinking perhaps removing the first stage inside red box,
I have seen circuit that only include the second sampling stage

 

[CDRIVE]

Ever hear the expression "That's like comparing Apples & Pears"? Well there's no Pears in this Sample & Hold video but there are Apples.

Here's a link to the LF398N that he mentions near the end of the vid.

BTW: I was surprised to find quite a few S & H Circuits that employed JFETs but as stated by Alec the Gate requires a negative voltage with respect to the Source to switch them off.

Chris

 

[AFex54]

Ever hear the expression "That's like comparing Apples & Pears"? Well there's no Pears in this Sample & Hold video but there are Apples.

Here's a link to the LF398N that he mentions near the end of the vid.

BTW: I was surprised to find quite a few S & H Circuits that employed JFETs but as stated by Alec the Gate requires a negative voltage with respect to the Source to switch them off.

Chris

I was looking for one of those sample and hold chips in the beginning but I couldnt find any available.
but I think now even my diode idea would be unnecessary (it would cause a voltage drop anyway right?),
in this even simpler circuit the switch could be my keyboard key, the typical first voltage follower you see in S&H circuits is absent but its not necessary in the case of the noise toasters CV input, which we established a few months ago.

 

[Alec_t]

The diode in post #6 will prevent the flow of opamp input bias current to ground/negative rail (unless you have some other path for that), and will also prevent the sampling cap voltage from decaying.
Have you considered using a CD4052 or similar?

 

[CDRIVE]

Now I'm really confused. Are you implying that your keyboard keys pass analog signals?

Chris

 

[AFex54]

Now I'm really confused. Are you implying that your keyboard keys pass analog signals?

Chris

they pass my control voltage? I was implying the DG403 was simply a mechanical switch (a keyboard key)

 

[CDRIVE]

If you're saying that your keyboard controls a DG403 then that was a Struther Martin moment.

Chris

 

[AFex54]

The diode in post #6 will prevent the flow of opamp input bias current to ground/negative rail (unless you have some other path for that), and will also prevent the sampling cap voltage from decaying.
Have you considered using a CD4052 or similar?

now im also confused,
preventing the sampling cap voltage from decaying? isnt that what 'holding' a sample is?
and the diode preventing the flow to ground, firstly i dont see the path to ground in any S&H circuit from the diode,
and I dont see how an open switch wouldnt prevent the flow aswell?
sorry about all these question, this subject is becoming more and more complicated the more I enquire

 

[AFex54]

If you're saying that your keyboard controls a DG403 then that was a Struther Martin moment.

Chris

?
in place of the DG403 would be the mechanical switch, there is no DG403.
the only thing about that circuit that Is important is the fact that there is no voltage follower before the switch like in most other sample and hold circuits,
the signal from my keyboard could go straight into the sampling stage
allowing the keyboard keys to perform the switching,
no need for an additional switch, such as a JFET.
i can understand how all this could be misunderstoof, there is a LOT going in during a keypress.
If you still arent sure what I mean I will just draw up a complete diagram of the synthesizer CV keyboard

 

[CDRIVE]

I think you need to review
This

Chris

 

[Alec_t]

preventing the sampling cap voltage from decaying? isnt that what 'holding' a sample is?

Up to a point, yes. But unless you can get the voltage down again your circuit becomes just a peak detector. With the diode in circuit you couldn't measure a low voltage signal amplitude that follows a high voltage signal amplitude.

I dont see how an open switch wouldnt prevent the flow aswell?

It would prevent flow; which is why there would need to be an alternate path, which isn't shown in post #6.

 

[CDRIVE]

now im also confused,
preventing the sampling cap voltage from decaying? isnt that what 'holding' a sample is?

Yes but the next time a sample is taken the cap voltage must follow the analog signal. If the signal at that moment is more positive than the previous sample the cap needs to charge more positive. On the other hand if the signal went less positive the cap has to discharge back into the buffer amplifier. The link I posted shows a good scope plot that makes the theory of operation very clear.

Here's a complete Tutorial

Chris

 

[AFex54]

Up to a point, yes. But unless you can get the voltage down again your circuit becomes just a peak detector. With the diode in circuit you couldn't measure a low voltage signal amplitude that follows a high voltage signal amplitude.
It would prevent flow; which is why there would need to be an alternate path, which isn't shown in post #6.

ok yeah that makes sense

 

[AFex54]

I think you need to review
This

Chris

im not sure if you understand what I mean when I say I just need a hold circuit.
In the typical S&H a JFET could allow independant control of sampling,
so an AC input could be sampled at any point from peak to peak,
I dont need this, I just need to maintain the DC input from the keyboard once the key is released .
in the red box is 1 key from the existing keyboard , there are 14 in total

 

[(*steve*)]

What will cause that voltage to fall back to zero?

What are you actually trying to do?

If you can explain it, the solution may not be what you're looking at.