Yes, but the single chip versions are just cut-down versions
of the same chips, without the high speed chip interconnects.
Makes it sound like they invented the concept!
Actually, other chip designers have known for years that it
wasn't possible to keep making single cores faster, and to
get more compute power, have been producing multi-core chips.
No idea what that's got to do with the discussion, but amnyway...
There are indeed times when you specifically don't want all the
cores busy. If you have an important single-threaded task you
need to complete quickly, even if you have enough other work to
keep the other cores busy, you'll do this by powering down some
of the other cores so the important single-threaded task can be
put onto a core which is cranked up to max speed (and hence max
power consumption), which you can't do on all cores at once.
However, when you want highest total throughput, then you want
to run all cores, even though you can't do so at max speed of
any one of them, because you would exceed the thermal capabilities
of the die. This all implies a kernel level thread scheduler which
is more intelligent than is commonly found in x86 based OS's today,
although not in Enterprise OS's. A power-aware scheduler will keep
an eye on the utilisation of the cores, and switch off cores when
there isn't a sustained workload to keep them all busy.
And this:
http://www.theregister.co.uk/2009/06/01/amd_launches_istanbul/
"The Istanbul Opterons contain 904 million transistors, which consist
of six cores, each with 64 KB of L1 data cache, 64 KB of L1
instruction cache, and 512 KB of L2 cache per core. The chip, which is
implemented in a 45 nanometer silicon-on-insulator process and
manufactured by AMD's fab spinoff, GlobalFoundries, in its Dresden,
Germany fab. Each chip also has 6 MB of L3 cache that is shared by all
of the cores..."
Folks seem to be dumping parallel front-side busses for multiple
serial interfaces, which will allow many independent DRAM and other
i/o ports.
The front-side bus went away for the reason I said earlier.
The switch to serial interfaces is for an interesting reason...
DRAM has been getting faster and faster, but that limits the
length of a parallel bus, and it reached the point where you
couldn't get more than 2 or 4 DIMMs running at max speed,
because any additional DIMMs are too far away from the processor
for the bus speed. The switch to serial interfaces (FBDIMMs)
removes the parallel bus data skewing problem, and it's easier
to get a serial bit rate running an order of magnitude faster
than it is to recover skewed data from a parallel bus. Serial
busses can be much longer, which means you can physically
connect out to more FBDIMMs. FBDIMMs are more power hungry though.
Another technique which is being used is serial interface from
the CPU same as FBDIMMs but conversion to parallel DIMMs right
next to the DIMMs. This gives the advantages of being able to
position DIMMs more than an inch or two from the chip as with
FBDIMMs and get full speed, but with the lower cost and lower
power of parallel DIMMs, although you still have higher latency.
(This parallel bus data skewing is also the reason the parallel
SCSI and parallel ATA interfaces have both gone serial. The
SCSI vendors spent a while trying to get Ultra640 SCSI working,
before giving up and deciding serial SCSI was the way forward.)
Sharing a central cache sure makes processor management easier.
I think all multi-core chips have always done that, except a few
strange Intel ones where they just shoe-horned two dies into one
package to get something to market early.
] Consider a system that has an
