Andrew said:
Interupts are not required since you can do that communications by
round-robin.
So all CPUs will spend their idle time sniffing this common memory?
Is this memory extensible so that, when it's full, the memory block
can be expanded? If it's expanded, who does the expansion? When
it's expanded, how do the other CPUs detect that the block is no
longer the size it used to be? And where will that block be
located? Moving it around would cause grey hairs to grow on the
bit gods.
You just need a fixed shared memory area with a separate
word/block/register for each core.
It can't be fixed. If a new piece of data is needed in future
implementations, the area has to be able to expand and contract.
Some of requests could be
implemented by the cores setting a request-to-talk bit in a hardware
register.
Whose hardware register?
An alternative is serial links between the cores. This has
to be defined in the high level design of the hardware.
This sounds like the common memory is far away from each CPU
which means a latency of updating data. So there has to be
a mechanism that tells other CPUs that one of them is
writing a piece of data. If two CPUs are writing the same
piece, who wins? If one is writing while another is reading
the same piece of data, which bits are the "real" data?
And how to the two (or 3 or 4 or...n) decide which data
is the "right" data? Note that the last write does not
necessarily have to be the correct data.
There is a second priority interrupt on the OS core - watch dog timer.
Can you think of any scenarios where this timer has to have a higher
priority than the read/write to the common memory of the system?
Probably via that core's shared memory area.
that's not soon enough.
On chip shared ram is needed. it could be off chip but that is slow.
Exactly. think about that.
Multi-core systems are very complex.
Yep which is why a master/slave concept cannot work well for
any general timesharing. I suppose a dedicated system (where
one, and only one, thing is done may be able to work but that
has a completely different set of problems.
One of the reasons that the chip manufactures can sell new chips with
faster clock speeds.
Even if the CPU runs faster than the speed of light but it still cannot
cooperate if all the other CPUs match its speed. If there is a slower
mechanism in the mix, all fast CPUs will be waiting for it to "catch
up". this goes back to problem of having n CPUs in cpu-wait before
they can execute their assigned tasks.
/BAH
