Debouncing....at About 1Mhz

[Jim Thompson]

On Sun, 11 Nov 2007 07:56:21 -0800, John Larkin
[snip]

I was also thinking that the origical hysteresis idea was OK except
that the hyst band of cmos schmitts is poorly defined. That's fixable
by defining it better, namely by adding additional hysteresis. The
numbers ought to work.

John

Damn...that's right...This is freakn scope trigger tech...
I didn't notice.
Bummer... I'm reinventing the wheel again.

Now I'm wondering if I could have cheated and looked up oscilloscope
trigger circuit patents to dodge a whole lot of dinking with gates, D
ff's and one shots.
There should be ooodles of trigger art since the invention of the
oscilloscope.

Well, DUH! My circuit trips on the first edge and ignores all others
"until sweep is complete"... it's called BLANKING ;-)

What to do.....
Use time sifting through mountains of patents
versus
use time designing from scratch..


D from BC

...Jim Thompson

 

[John Fields]

[snipped .asc file for less scrolling]

Yup ..this is in the same solution family.

Without running a sim, I can see how this works..
It's comparator reference level shifting by differentiator.
The differentiator pops the - input into oblivion for a time which
makes the comparator dead and that's how the fuzzy edges are skipped.

---
Actually, the input signal is attenuated so that it toggles between
1.5V and 3.5V, (so that one of the inputs is always below the common
mode limit) and the differentiator forces the inverting input of the
comparator to a little bit higher/lower than the rail with the
opposite polarity of the input signal, which keeps the input chatter
away from the switching point until the cap discharges.
---

Nice....

---
Thanks!
---

Uses single output op amps.
---
Comparators.
---

Single device prop delay.
1 IC solution.
Fast.

---
Yup. Tpd = 8ns worst case over temp., 6.5 ns at room temp.
---

I like my 80% baked solution on
http://www.members.shaw.ca/chainsaw/SED/compsolution.jpg

---
Yeah, not bad for a newbie

Not bad at all, for that matter.
---

The first op amp
---
comparator
---

is unstable. When an edge crosses the threshold the
comparator locks up fast due to a local positive feedback loop.
The input signal probably can't compete with this

---
Probably ???
You're the designer, how come you don't know for sure?
---

and therefore no
race condition exists and it's unlikely the timing will fault.
(Yes...I got scared by JL posts of asynch hairballs. )

---
Don't be afraid. JL is a good circuit designer, but he has his own
agenda.
---

JF, I see a 2 comparator delay in disabling the first comparator.
I have to wonder if some glitch could still slip through..

---
It might, but it would have to be pretty damn fast.

If you know what the signal looks like, worst case, during the early
switching interval, or if you can spec the glitch time, then maybe
we can come up with a bulletproof solution for you.

Do/can you?

 

[John Larkin]

Yeah. I hate to write ECOs.

John

 

[John Fields]

On Sat, 10 Nov 2007 19:35:26 -0800, John Larkin

On Sat, 10 Nov 2007 19:55:00 -0600, John Fields

On Sat, 10 Nov 2007 14:40:51 -0700, Jim Thompson

On Sat, 10 Nov 2007 11:42:31 -0800, John Larkin

On Sat, 10 Nov 2007 11:57:19 -0700, Jim Thompson

[snip]

Now please present us with your "solution" with component names and
values and I'll simulate it side-by-side with my design.


I rarely simulate. Design is the reverse of simulation. Design forces
the desired results, so why simulate?

[snip]

So you've been converted to the Bob Pease school of hand waving ?

My POV: Design puts the idea onto paper. Simulation proves that what
is on the paper really works. But simulators don't "design". In my
business, simulation "proof" is required for each and every process
corner, otherwise the customer doesn't "buy".

---
I used to be in Larkin's corner, defending "build and test" over
"simulate", but after writing a few simulators to solve specific
problems posed here on sed, which couldn't be solved, practically,
any other way, I decided to lay down my wire-wrap gun until the
machine worked in the computer.

Then, along came wonderful, free LTSPICE.

I've designed stuff using it which I never had to physically build,
but which worked and which I got paid for, which is a joy.

A feeling I'm sure you enjoyed before I did.

An asynchronous circuit like this, and even moreso some of the others
that gave been posted, has internal delays and is subject to all
possible timings in the chatter zone. Spice can't really test all the
possible combinations of timings. You can generate a chatter
simulator, but you can't be sure its deterministic behavior represents
the real world of arbitrary timings. Complex async circuits can have
low-probability picosecond-wide windows of hazard.

John

I got inspired by that differentiator + schmitt invertor sketch of
yours.
The idea was to move the signal into the hysteresis levels.
I though I'd try doing the opposite..Moving the hystersis levels to
meet the signal..

Check out my hysteretic hairball! :O *
http://www.members.shaw.ca/chainsaw/SED/compsolution.jpg
569Kb

Yeah, I was thinking along those lines. This is a "feed-beside" sort
of concept, a brutally fast forward path, with slower tweaks off to
the side to fix the low-speed defects. This was the concept Tek used
in their 7000 series oscilloscopes.

I was also thinking that the origical hysteresis idea was OK except
that the hyst band of cmos schmitts is poorly defined. That's fixable
by defining it better, namely by adding additional hysteresis. The
numbers ought to work.

John

Damn...that's right...This is freakn scope trigger tech...
I didn't notice.
Bummer... I'm reinventing the wheel again.

Now I'm wondering if I could have cheated and looked up oscilloscope
trigger circuit patents to dodge a whole lot of dinking with gates, D
ff's and one shots.
There should be ooodles of trigger art since the invention of the
oscilloscope.

What to do.....
Use time sifting through mountains of patents
versus
use time designing from scratch..

---
If it's for your own enlightenment, design from scratch. That way,
if you succeed, the thrill of discovery will be yours as much as it
was for whoever came up with it first, if you weren't.

And, if you fail, you will have, at least, fought the good fight.

 

[Jim Thompson]

On Sun, 11 Nov 2007 01:32:07 -0800, D from BC

On Sat, 10 Nov 2007 19:35:26 -0800, John Larkin

On Sat, 10 Nov 2007 19:55:00 -0600, John Fields

On Sat, 10 Nov 2007 14:40:51 -0700, Jim Thompson

On Sat, 10 Nov 2007 11:42:31 -0800, John Larkin

On Sat, 10 Nov 2007 11:57:19 -0700, Jim Thompson

[snip]

Now please present us with your "solution" with component names and
values and I'll simulate it side-by-side with my design.


I rarely simulate. Design is the reverse of simulation. Design forces
the desired results, so why simulate?

[snip]

So you've been converted to the Bob Pease school of hand waving ?

My POV: Design puts the idea onto paper. Simulation proves that what
is on the paper really works. But simulators don't "design". In my
business, simulation "proof" is required for each and every process
corner, otherwise the customer doesn't "buy".

---
I used to be in Larkin's corner, defending "build and test" over
"simulate", but after writing a few simulators to solve specific
problems posed here on sed, which couldn't be solved, practically,
any other way, I decided to lay down my wire-wrap gun until the
machine worked in the computer.

Then, along came wonderful, free LTSPICE.

I've designed stuff using it which I never had to physically build,
but which worked and which I got paid for, which is a joy.

A feeling I'm sure you enjoyed before I did.

An asynchronous circuit like this, and even moreso some of the others
that gave been posted, has internal delays and is subject to all
possible timings in the chatter zone. Spice can't really test all the
possible combinations of timings. You can generate a chatter
simulator, but you can't be sure its deterministic behavior represents
the real world of arbitrary timings. Complex async circuits can have
low-probability picosecond-wide windows of hazard.

John

I got inspired by that differentiator + schmitt invertor sketch of
yours.
The idea was to move the signal into the hysteresis levels.
I though I'd try doing the opposite..Moving the hystersis levels to
meet the signal..

Check out my hysteretic hairball! :O *
http://www.members.shaw.ca/chainsaw/SED/compsolution.jpg
569Kb

Yeah, I was thinking along those lines. This is a "feed-beside" sort
of concept, a brutally fast forward path, with slower tweaks off to
the side to fix the low-speed defects. This was the concept Tek used
in their 7000 series oscilloscopes.

I was also thinking that the origical hysteresis idea was OK except
that the hyst band of cmos schmitts is poorly defined. That's fixable
by defining it better, namely by adding additional hysteresis. The
numbers ought to work.

John

Damn...that's right...This is freakn scope trigger tech...
I didn't notice.
Bummer... I'm reinventing the wheel again.

Now I'm wondering if I could have cheated and looked up oscilloscope
trigger circuit patents to dodge a whole lot of dinking with gates, D
ff's and one shots.
There should be ooodles of trigger art since the invention of the
oscilloscope.

What to do.....
Use time sifting through mountains of patents
versus
use time designing from scratch..

---
If it's for your own enlightenment, design from scratch. That way,
if you succeed, the thrill of discovery will be yours as much as it
was for whoever came up with it first, if you weren't.

And, if you fail, you will have, at least, fought the good fight.

There's nothing quite so satisfying as building something yourself and
having it work... almost as good as an orgasm ;-)

...Jim Thompson

 

[D from BC]

On Sun, 11 Nov 2007 07:56:21 -0800, John Larkin
[snip]

I was also thinking that the origical hysteresis idea was OK except
that the hyst band of cmos schmitts is poorly defined. That's fixable
by defining it better, namely by adding additional hysteresis. The
numbers ought to work.

John

Damn...that's right...This is freakn scope trigger tech...
I didn't notice.
Bummer... I'm reinventing the wheel again.

Now I'm wondering if I could have cheated and looked up oscilloscope
trigger circuit patents to dodge a whole lot of dinking with gates, D
ff's and one shots.
There should be ooodles of trigger art since the invention of the
oscilloscope.

Well, DUH! My circuit trips on the first edge and ignores all others
"until sweep is complete"... it's called BLANKING ;-)

What to do.....
Use time sifting through mountains of patents
versus
use time designing from scratch..


D from BC

...Jim Thompson

lol... When I first posted this problem (Debouncing....at About 1Mhz).
I did suspect it was a classic problem with a known classic solution.
I just didn't think of in what... Oscilloscopes! Doh!

About all schematics...

The thing I don't like about the use of comparator solutions is a
bucketload of resistors are needed as seen in my design and JF's
design.

The JL based 2 D ff + one shot I posted has a lower parts count and
the same goes for your (Jim) recently posted schematics.
All with only 1 Dff prop delay off the primary pos edge and primary
neg edge.

It looks like it's down to D flip flops vs comparators.

I like the parts count of Dff based designs and I'm going to look at'm
closer..


D from BC

 

[JosephKK]

Jim Thompson [email protected] posted to
sci.electronics.design:

On Sat, 10 Nov 2007 18:03:07 -0700, Jim Thompson

On Sat, 10 Nov 2007 16:19:54 -0800, John Larkin
[snip]

Your Sysreset sets Q high, but your sim starts with Q low. Why?

John


The default set-ups included FF initial conditions Q=0. If I
uncheck that box it starts, as would be expected, with Q=1.

...Jim Thompson

Well, run that. It's more interesting.

John

Yep. It takes one cycle for the output to be correct.

...Jim Thompson


It seems to work, but it's awfully convoluted. It would be, for me,
like one of those things that I designed but that I can barely
understand myself; there are too many possible states, and the
dflop clock sometimes comes from the input, and sometimes comes
from the input xored with the internal delay.

Think of the XOR as a device that is switched from being an inverter
to being a buffer. The switching does not occur while clock (input)
edges are present.

And the input can chatter, or it

Does nothing after the first transition... it's an edge-triggered
flop.

could be a single edge of either polarity. All those conditions
have to be proven to work, and proving it is too much work.

I avoid clever stuff like that, in hardware and in software. Sorry,
but I prefer my first circuit, because it's a lot easier to
understand.

John

When I feel confused I drinks a glass of wine ;-)

...Jim Thompson

With PREbar functional....

http://www.analog-innovations.com/SED/AlternatingEdge-Unobtanium.pdf

I use that inverter/buffer characteristic of the XOR a lot...

Say I have an 8GHz (Johnson-type) divider chain down to 125MHz...
object to create single-side-band. (Mixed-mode to boot... CML down
to around 500MHZ, then CMOS.)

Since it's a Johnson counter with no set or reset, how do I
guarantee the phase relationship of the 8GHz to the 125MHz?

Answer, I don't.

What I did was measure literally, using a cell aptly named
"WhosOnFirst.sch" (*) and invert as needed.

(*) No one got the joke. Youngsters :-(

...Jim Thompson

Damnit, are you trying to make feel old.
Today is catching.

 

[Jim Thompson]

Jim Thompson [email protected] posted to
sci.electronics.design:
[snip]

What I did was measure literally, using a cell aptly named
"WhosOnFirst.sch" (*) and invert as needed.

(*) No one got the joke. Youngsters :-(

...Jim Thompson

Damnit, are you trying to make feel old.
Today is catching.

Sno-o-o-ort!

...Jim Thompson

 

[JosephKK]

ChairmanOfTheBored [email protected] posted to
sci.electronics.design:

On Sat, 10 Nov 2007 14:40:51 -0700, Jim Thompson

On Sat, 10 Nov 2007 11:42:31 -0800, John Larkin

On Sat, 10 Nov 2007 11:57:19 -0700, Jim Thompson

[snip]

Now please present us with your "solution" with component names
and values and I'll simulate it side-by-side with my design.


I rarely simulate. Design is the reverse of simulation. Design
forces the desired results, so why simulate?

[snip]

So you've been converted to the Bob Pease school of hand waving
?

My POV: Design puts the idea onto paper. Simulation proves that
what
is on the paper really works. But simulators don't "design". In
my business, simulation "proof" is required for each and every
process corner, otherwise the customer doesn't "buy".

---
I used to be in Larkin's corner, defending "build and test" over
"simulate", but after writing a few simulators to solve specific
problems posed here on sed, which couldn't be solved, practically,
any other way, I decided to lay down my wire-wrap gun until the
machine worked in the computer.

Then, along came wonderful, free LTSPICE.

I've designed stuff using it which I never had to physically build,
but which worked and which I got paid for, which is a joy.

A feeling I'm sure you enjoyed before I did.

I still find it amazing that after benchtesting, I can see that I
forgot to include parasitics in a circuit model.
After including the parasitics in the model, I get the sim waveforms
that I see on the scope

Bouncing between model and bench and model and bench can build a
good model.

Forgetting the parasitic aspects of circuit configurations as well
as
the individual components themselves is the main reason why those
that do
not like simulators hate to use them. They fail at doing so.

A good sim will match the real circuit just about exactly.
Considering
the elements of the software used to make a sim a sim, it would have
to.

It's like Ohm's Law. The rules are the rules, and if you are
following
them, your calculator will display the proper figure in its
mantissa.

Sims work great. I love 'em. When they don't match the real data
gathered, and the engineer goes about the chore of finding out why,
he
should also increase his education in the field as a result. A
proper
sim will always match the real data. If it doesn't, something was
left
out. It is like a puzzle.

Goodness, 4 paragraphs and not a curse word in it. You even seem to
make sense this time. If you post like this you could be welcome
here.

 

[JosephKK]

D from BC [email protected] posted to sci.electronics.design:

On Sat, 10 Nov 2007 14:40:51 -0700, Jim Thompson

On Sat, 10 Nov 2007 11:42:31 -0800, John Larkin

On Sat, 10 Nov 2007 11:57:19 -0700, Jim Thompson

[snip]

Now please present us with your "solution" with component names
and values and I'll simulate it side-by-side with my design.


I rarely simulate. Design is the reverse of simulation. Design
forces the desired results, so why simulate?

[snip]

So you've been converted to the Bob Pease school of hand waving
?

My POV: Design puts the idea onto paper. Simulation proves that
what
is on the paper really works. But simulators don't "design". In
my business, simulation "proof" is required for each and every
process corner, otherwise the customer doesn't "buy".

---
I used to be in Larkin's corner, defending "build and test" over
"simulate", but after writing a few simulators to solve specific
problems posed here on sed, which couldn't be solved, practically,
any other way, I decided to lay down my wire-wrap gun until the
machine worked in the computer.

Then, along came wonderful, free LTSPICE.

I've designed stuff using it which I never had to physically build,
but which worked and which I got paid for, which is a joy.

A feeling I'm sure you enjoyed before I did.

An asynchronous circuit like this, and even moreso some of the
others that gave been posted, has internal delays and is subject to
all possible timings in the chatter zone. Spice can't really test
all the possible combinations of timings. You can generate a chatter
simulator, but you can't be sure its deterministic behavior
represents the real world of arbitrary timings. Complex async
circuits can have low-probability picosecond-wide windows of hazard.

John

I got inspired by that differentiator + schmitt invertor sketch of
yours.
The idea was to move the signal into the hysteresis levels.
I though I'd try doing the opposite..Moving the hystersis levels to
meet the signal..

Check out my hysteretic hairball! :O *
http://www.members.shaw.ca/chainsaw/SED/compsolution.jpg
569Kb

Notes:
* Top wave is the inverting input of U1.
(It's a cool waveform. 4 levels! )
* Prop delay is from a single device at less than 10nS.
* This can be a 1 chip solution with a fast dual comparator.
* I picked the LT1713 just because it's fast.
* The integrator + U2 could be replaced by some 'one shot' IC
solution * This circuit is not quite baked because I skipped on the
math and did best guesses on the resistor values.

With some tweaking, I think this might be a good circuit.

D from BC

I would say the idea is on target the the implementation is
excessively partsy. Simplify.

 

[Jim Thompson]

ChairmanOfTheBored [email protected] posted to
sci.electronics.design:
[snip]

Forgetting the parasitic aspects of circuit configurations as well
as
the individual components themselves is the main reason why those
that do
not like simulators hate to use them. They fail at doing so.

A good sim will match the real circuit just about exactly.
Considering
the elements of the software used to make a sim a sim, it would have
to.

It's like Ohm's Law. The rules are the rules, and if you are
following
them, your calculator will display the proper figure in its
mantissa.

Sims work great. I love 'em. When they don't match the real data
gathered, and the engineer goes about the chore of finding out why,
he
should also increase his education in the field as a result. A
proper
sim will always match the real data. If it doesn't, something was
left
out. It is like a puzzle.

Goodness, 4 paragraphs and not a curse word in it. You even seem to
make sense this time. If you post like this you could be welcome
here.

Amazing! Indeed such commentary is very welcome here.

...Jim Thompson

 

[ChairmanOfTheBored]

On Sat, 10 Nov 2007 18:03:07 -0700, Jim Thompson

On Sat, 10 Nov 2007 16:19:54 -0800, John Larkin
[snip]

Your Sysreset sets Q high, but your sim starts with Q low. Why?

John


The default set-ups included FF initial conditions Q=0. If I uncheck
that box it starts, as would be expected, with Q=1.

...Jim Thompson

Well, run that. It's more interesting.

John

Yep. It takes one cycle for the output to be correct.

...Jim Thompson


It seems to work, but it's awfully convoluted. It would be, for me,
like one of those things that I designed but that I can barely
understand myself; there are too many possible states, and the dflop
clock sometimes comes from the input, and sometimes comes from the
input xored with the internal delay.

Think of the XOR as a device that is switched from being an inverter
to being a buffer. The switching does not occur while clock (input)
edges are present.

And the input can chatter, or it

Does nothing after the first transition... it's an edge-triggered
flop.

could be a single edge of either polarity. All those conditions have
to be proven to work, and proving it is too much work.

I avoid clever stuff like that, in hardware and in software. Sorry,
but I prefer my first circuit, because it's a lot easier to
understand.

John

When I feel confused I drinks a glass of wine ;-)

...Jim Thompson

One of the great engineering virtues is laziness. I consider a circuit
or a piece of code or a mechanism and say "that's going to be way too
much work" so I put it off for a while, or talk to somebody about it.
Usually something simpler emerges. Too many people, cursed with excess
energy, just plow ahead and implement the first idea they have. And
when it turns out to have bugs, as complex things will, they add stuff
to repair the bugs.

John

Must be what happened to you.

 

[JosephKK]

D from BC [email protected] posted to sci.electronics.design:

On Sat, 10 Nov 2007 14:40:51 -0700, Jim Thompson

On Sat, 10 Nov 2007 11:42:31 -0800, John Larkin

On Sat, 10 Nov 2007 11:57:19 -0700, Jim Thompson

[snip]

Now please present us with your "solution" with component names
and values and I'll simulate it side-by-side with my design.


I rarely simulate. Design is the reverse of simulation. Design
forces the desired results, so why simulate?

[snip]

So you've been converted to the Bob Pease school of hand waving
?

My POV: Design puts the idea onto paper. Simulation proves that
what
is on the paper really works. But simulators don't "design". In
my business, simulation "proof" is required for each and every
process corner, otherwise the customer doesn't "buy".

---
I used to be in Larkin's corner, defending "build and test" over
"simulate", but after writing a few simulators to solve specific
problems posed here on sed, which couldn't be solved, practically,
any other way, I decided to lay down my wire-wrap gun until the
machine worked in the computer.

Then, along came wonderful, free LTSPICE.

I've designed stuff using it which I never had to physically build,
but which worked and which I got paid for, which is a joy.

A feeling I'm sure you enjoyed before I did.

It took me MANY years to trust simulators. Initially even bipolar
device models were bad.

But I still "design" by first "sketching", even if the "sketching"
does use a schematic capture program... I'm faster that way, no
erasing... drag stuff around... such fun!

Then I simulate.

...Jim Thompson

I still sketch for the tough problems.
That gives me the freedom to express the problem in any fashion.
If drawing cartoons of a little choo choo train stuck in a valley
helps to solve the circuit ... great!

Also, I think I can move my pen faster than a mouse.
D from BC

Yeah, but my pen (when using the tablet) can move a symbol or even a
group of symbols.

 

[John Fields]

Looks pretty good. The only hazard I can see is that a very fast spike
can blow through the first comparator before the second one has time
to come back around. That's a hazard with most all comparators that
have external hysteresis.

---
These have internal hysteresis but, after just a cursory glance, I
haven't figured out how to make that work in this application.
---

That's only a problem if the input can in fact have such fast spikes,
which in this case maybe it can't.

---
But maybe it can..

I've asked the OP
to disclose what the input signal looks like, so maybe we'll be
graced with an answer soon.

 

[D from BC]

On Sun, 11 Nov 2007 07:56:21 -0800, John Larkin

On Sun, 11 Nov 2007 01:32:07 -0800, D from BC

Check out my hysteretic hairball! :O *
http://www.members.shaw.ca/chainsaw/SED/compsolution.jpg
569Kb

Yeah, I was thinking along those lines. This is a "feed-beside" sort
of concept, a brutally fast forward path, with slower tweaks off to
the side to fix the low-speed defects. This was the concept Tek used
in their 7000 series oscilloscopes.

I was also thinking that the origical hysteresis idea was OK except
that the hyst band of cmos schmitts is poorly defined. That's fixable
by defining it better, namely by adding additional hysteresis. The
numbers ought to work.

[snipped .asc file for less scrolling]

Yup ..this is in the same solution family.

Without running a sim, I can see how this works..
It's comparator reference level shifting by differentiator.
The differentiator pops the - input into oblivion for a time which
makes the comparator dead and that's how the fuzzy edges are skipped.

---
Actually, the input signal is attenuated so that it toggles between
1.5V and 3.5V, (so that one of the inputs is always below the common
mode limit) and the differentiator forces the inverting input of the
comparator to a little bit higher/lower than the rail with the
opposite polarity of the input signal, which keeps the input chatter
away from the switching point until the cap discharges.
---

Nice....

---
Thanks!
---

Uses single output op amps.
---
Comparators.
---

Single device prop delay.
1 IC solution.
Fast.

---
Yup. Tpd = 8ns worst case over temp., 6.5 ns at room temp.
---

I like my 80% baked solution on
http://www.members.shaw.ca/chainsaw/SED/compsolution.jpg

---
Yeah, not bad for a newbie

Not bad at all, for that matter.
---

The first op amp
---
comparator
---

is unstable. When an edge crosses the threshold the
comparator locks up fast due to a local positive feedback loop.
The input signal probably can't compete with this

---
Probably ???
You're the designer, how come you don't know for sure?
---

and therefore no
race condition exists and it's unlikely the timing will fault.
(Yes...I got scared by JL posts of asynch hairballs. )

---
Don't be afraid. JL is a good circuit designer, but he has his own
agenda.
---

JF, I see a 2 comparator delay in disabling the first comparator.
I have to wonder if some glitch could still slip through..

---
It might, but it would have to be pretty damn fast.

If you know what the signal looks like, worst case, during the early
switching interval, or if you can spec the glitch time, then maybe
we can come up with a bulletproof solution for you.

Do/can you?
---

In my circuit the first comparator is disabled by 1 comparator delay.

Thanks for the complement..

I hurt my brain thinking up that circuit..
That's why I have 'op amp' and 'comparator' all mixed up

I don't know if I could have thought of this circuit without seeing
JL's RC+schmitt circuit.

You asked how long it takes to get through...
(You mean the tp performance..)

On
http://www.members.shaw.ca/chainsaw/SED/compsolution.jpg

The desired output edge forms after only 1 comparator delay.

Not only is the edge formed by crossing a threshold but also
reinforced by regenerative feedback that also starts after 1
comparator delay too.

It probably has the same tp performance as your circuit when using
same comparators.

The difference might be with input overdrive.

I recall seeing input overdrive specs on comparator datasheets.
The more overdrive...the less tp.
With positive feedback...there's overdrive
So I suspect the positive feedback will push the comparator to react
quicker.

D from BC

 

[John Fields]

On Sun, 11 Nov 2007 07:56:21 -0800, John Larkin

On Sun, 11 Nov 2007 01:32:07 -0800, D from BC

On Sat, 10 Nov 2007 19:35:26 -0800, John Larkin

On Sat, 10 Nov 2007 19:55:00 -0600, John Fields

On Sat, 10 Nov 2007 14:40:51 -0700, Jim Thompson

On Sat, 10 Nov 2007 11:42:31 -0800, John Larkin

On Sat, 10 Nov 2007 11:57:19 -0700, Jim Thompson

[snip]

Now please present us with your "solution" with component names and
values and I'll simulate it side-by-side with my design.


I rarely simulate. Design is the reverse of simulation. Design forces
the desired results, so why simulate?

[snip]

So you've been converted to the Bob Pease school of hand waving ?

My POV: Design puts the idea onto paper. Simulation proves that what
is on the paper really works. But simulators don't "design". In my
business, simulation "proof" is required for each and every process
corner, otherwise the customer doesn't "buy".

---
I used to be in Larkin's corner, defending "build and test" over
"simulate", but after writing a few simulators to solve specific
problems posed here on sed, which couldn't be solved, practically,
any other way, I decided to lay down my wire-wrap gun until the
machine worked in the computer.

Then, along came wonderful, free LTSPICE.

I've designed stuff using it which I never had to physically build,
but which worked and which I got paid for, which is a joy.

A feeling I'm sure you enjoyed before I did.

An asynchronous circuit like this, and even moreso some of the others
that gave been posted, has internal delays and is subject to all
possible timings in the chatter zone. Spice can't really test all the
possible combinations of timings. You can generate a chatter
simulator, but you can't be sure its deterministic behavior represents
the real world of arbitrary timings. Complex async circuits can have
low-probability picosecond-wide windows of hazard.

John

I got inspired by that differentiator + schmitt invertor sketch of
yours.
The idea was to move the signal into the hysteresis levels.
I though I'd try doing the opposite..Moving the hystersis levels to
meet the signal..

Check out my hysteretic hairball! :O *
http://www.members.shaw.ca/chainsaw/SED/compsolution.jpg
569Kb

Yeah, I was thinking along those lines. This is a "feed-beside" sort
of concept, a brutally fast forward path, with slower tweaks off to
the side to fix the low-speed defects. This was the concept Tek used
in their 7000 series oscilloscopes.

I was also thinking that the origical hysteresis idea was OK except
that the hyst band of cmos schmitts is poorly defined. That's fixable
by defining it better, namely by adding additional hysteresis. The
numbers ought to work.

John


Damn...that's right...This is freakn scope trigger tech...
I didn't notice.
Bummer... I'm reinventing the wheel again.

Now I'm wondering if I could have cheated and looked up oscilloscope
trigger circuit patents to dodge a whole lot of dinking with gates, D
ff's and one shots.
There should be ooodles of trigger art since the invention of the
oscilloscope.

What to do.....
Use time sifting through mountains of patents
versus
use time designing from scratch..

---
If it's for your own enlightenment, design from scratch. That way,
if you succeed, the thrill of discovery will be yours as much as it
was for whoever came up with it first, if you weren't.

And, if you fail, you will have, at least, fought the good fight.

There's nothing quite so satisfying as building something yourself and
having it work... almost as good as an orgasm ;-)

 

[John Larkin]

On Sun, 11 Nov 2007 07:56:21 -0800, John Larkin
[snip]

I was also thinking that the origical hysteresis idea was OK except
that the hyst band of cmos schmitts is poorly defined. That's fixable
by defining it better, namely by adding additional hysteresis. The
numbers ought to work.

John


Damn...that's right...This is freakn scope trigger tech...
I didn't notice.
Bummer... I'm reinventing the wheel again.

Now I'm wondering if I could have cheated and looked up oscilloscope
trigger circuit patents to dodge a whole lot of dinking with gates, D
ff's and one shots.
There should be ooodles of trigger art since the invention of the
oscilloscope.

Well, DUH! My circuit trips on the first edge and ignores all others
"until sweep is complete"... it's called BLANKING ;-)

What to do.....
Use time sifting through mountains of patents
versus
use time designing from scratch..


D from BC

...Jim Thompson

lol... When I first posted this problem (Debouncing....at About 1Mhz).
I did suspect it was a classic problem with a known classic solution.
I just didn't think of in what... Oscilloscopes! Doh!

About all schematics...

The thing I don't like about the use of comparator solutions is a
bucketload of resistors are needed as seen in my design and JF's
design.

The JL based 2 D ff + one shot I posted has a lower parts count and
the same goes for your (Jim) recently posted schematics.
All with only 1 Dff prop delay off the primary pos edge and primary
neg edge.

It looks like it's down to D flip flops vs comparators.

I like the parts count of Dff based designs and I'm going to look at'm
closer..


D from BC

My first post, the quad xor + dff + rc, still looks like the simplest
and fastest circuit so far. It appears to be hazard free, too, at
least using cmos transmission-gate flipflops.

The last one I posted, 1 xor and 1 dflop and 1 rc, is sort of a hybrid
of my circuit and Jim's. It's not bad either. Too bad the really fast
tiny-logic flops don't generally have qbar.

John

 

[Michael A. Terrell]

There's nothing quite so satisfying as building something yourself and
having it work... almost as good as an orgasm ;-)

There are some around her who haven't experienced either. You can
tell, because they are always on edge.

--
Service to my country? Been there, Done that, and I've got my DD214 to
prove it.
Member of DAV #85.

Michael A. Terrell
Central Florida

 

[John Larkin]

I found, at least with 74HC' stuff, that I needed to delay the clock
flip-over as well... looked like SUAH timing was violated.

...Jim Thompson

This one looks OK to me. The rc keeps D from changing anywhere near
clock edges. The reason the clock goes back low is because qbar has
already flipped, and you can't take that back.

This makes a short (2 pd) positive clock blip every input transition,
or a whole mess of them when the input chatters. All of them clock the
"old" rc filtered level into the flop. It's close to my original
circuit, but uses your xor thing to eliminate the three dummy delay
stages.

This is close to minimal from a parts count standpoint. 4 parts
approaches 0 parts as design time approaches infinity.

John

 

[D from BC]

---
These have internal hysteresis but, after just a cursory glance, I
haven't figured out how to make that work in this application.
---


---
But maybe it can..

I've asked the OP
to disclose what the input signal looks like, so maybe we'll be
graced with an answer soon.

There won't be any razor thin spikes..
I believe your circuit will work just fine.

The bug I have with comparator solutions is the bucketload of
resistors needed. I hate smd layout

So Jim's Dff designs look good.


D from BC