Debouncing....at About 1Mhz

[John Larkin]

---
Hmm...

I guess you haven't gone to the trouble of running the simulation
that I provided.

Simulation can only show that an async circuit might work. It can't
prove that it always works. Your circuit is sufficiently complex and
tangled that it probably has several timing hazards. But it won't meet
the 10 ns limit, so it doesn't work to the OP's specs.


The Res Sox didn't like the Yankees, but they played them anyhow.
That's the game.

John

 

[John Larkin]

On Sat, 10 Nov 2007 07:16:19 -0800, John Larkin

On Sat, 10 Nov 2007 06:44:11 -0700, Jim Thompson

On Fri, 09 Nov 2007 20:23:00 -0800, John Larkin

On Sat, 10 Nov 2007 02:06:41 GMT, JosephKK

John Larkin [email protected] posted to
sci.electronics.design:

[snip]

Yes, there is a simple fix that allows reliable operation with
real-world cmos schmitts. It's sort of obvious.

John

If you think so build and test it, or SPICE it. Show us the results.

Hell, I've already done the only circuit that really works.

My circuit doesn't work? Sure it does. I captures the first
transition just as requested by the OP.

And includes the unobtainium "Delay" box, whose output splits into two
timing-critical paths, always an alarm in async logic. Finish the
design and we'll see.

[snip]

Unobtanium obtained...

http://www.analog-innovations.com/SED/AlternatingEdge-Unobtanium.pdf

Now please present us with your "solution" with component names and
values and I'll simulate it side-by-side with my design.

I rarely simulate. Design is the reverse of simulation. Design forces
the desired results, so why simulate?

The easy way would be to use an AC86 quad xor and an AC74 flipflop.
That would actually make the 10 ns prop delay in real life, but not
guaranteed over temperature. There are lots of faster parts around,
like NC7SZ86 (< 6 ns xor) and flipflops down to 1 ns... 74AUC1G74
would do. Using the tinies would of course require more cans, but
they're cheap, and the delay could be a single slower gate. The 1-gate
flops doen't have qbar, so you'd need to add an inverter before D if
you need straight-up output. Four tiny-logic cans max, if you really
need the speed.

So, easy way: 74AC86, 74AC74. The rc tau needs to be somewhat greater
than 100 ns and less than 500 ns (100 ns max bounce, 1 MHz rate) so go
for tau=220 ns, 330 ohms and 680 pF. This is a little tight on
discriminating the bounces from the period, and a serial L would help
a lot, as mentioned before; L = 39 uH should be about right. All
values are guessed, without mechanical assistance.

If you feel the worst-case AC logic delays are unacceptable, go with
the faster parts.

Otherwise you will henceforth known as John "BSA" Larkin.

"BSA" == Bull-Shit-Artist ;-)

You are being unnecessarily, and inaccurately, offensive. I've
designed a couple of hundred million dollars worth of
analog/digital/uP/firmware stuff so far, for some of the biggest
projects on the planet. My stuff works, and this circuit will work.

Simulate it, if you really need to.

John

Draw it as a schematic, and I will simulate it.

I already did. If you can't plug in my values, then don't. I have zero
interest in proving to you that my circuit will work.

John

 

[Jim Thompson]

On Sat, 10 Nov 2007 13:04:36 -0700, Jim Thompson
[snip]

Draw it as a schematic, and I will simulate it.

I already did. If you can't plug in my values, then don't. I have zero
interest in proving to you that my circuit will work.

John

QED ;-)

...Jim Thompson

 

[John Fields]

On Sat, 10 Nov 2007 12:22:57 -0600, John Fields

If you ever say anything funny, we'll let you know.

 

[John Fields]

On Sat, 10 Nov 2007 08:04:51 -0600, John Fields


The Res Sox didn't like the Yankees, but they played them anyhow.
That's the game.

 

[Jim Thompson]

On Sat, 10 Nov 2007 11:57:19 -0700, Jim Thompson
[snip]

Now please present us with your "solution" with component names and
values and I'll simulate it side-by-side with my design.

I rarely simulate. Design is the reverse of simulation. Design forces
the desired results, so why simulate?

[snip]

So you've been converted to the Bob Pease school of hand waving ?

My POV: Design puts the idea onto paper. Simulation proves that what
is on the paper really works. But simulators don't "design". In my
business, simulation "proof" is required for each and every process
corner, otherwise the customer doesn't "buy".

...Jim Thompson

 

[John Larkin]

On Sat, 10 Nov 2007 11:57:19 -0700, Jim Thompson
[snip]

Now please present us with your "solution" with component names and
values and I'll simulate it side-by-side with my design.

I rarely simulate. Design is the reverse of simulation. Design forces
the desired results, so why simulate?

[snip]

So you've been converted to the Bob Pease school of hand waving ?

My POV: Design puts the idea onto paper. Simulation proves that what
is on the paper really works. But simulators don't "design". In my
business, simulation "proof" is required for each and every process
corner, otherwise the customer doesn't "buy".

...Jim Thompson

Your Sysreset sets Q high, but your sim starts with Q low. Why?

John

 

[Jim Thompson]

On Sat, 10 Nov 2007 11:57:19 -0700, Jim Thompson
[snip]

Now please present us with your "solution" with component names and
values and I'll simulate it side-by-side with my design.


I rarely simulate. Design is the reverse of simulation. Design forces
the desired results, so why simulate?

[snip]

So you've been converted to the Bob Pease school of hand waving ?

My POV: Design puts the idea onto paper. Simulation proves that what
is on the paper really works. But simulators don't "design". In my
business, simulation "proof" is required for each and every process
corner, otherwise the customer doesn't "buy".

...Jim Thompson

Your Sysreset sets Q high, but your sim starts with Q low. Why?

John

The default set-ups included FF initial conditions Q=0. If I uncheck
that box it starts, as would be expected, with Q=1.

...Jim Thompson

 

[John Larkin]

On Sat, 10 Nov 2007 11:42:31 -0800, John Larkin

On Sat, 10 Nov 2007 11:57:19 -0700, Jim Thompson

[snip]

Now please present us with your "solution" with component names and
values and I'll simulate it side-by-side with my design.


I rarely simulate. Design is the reverse of simulation. Design forces
the desired results, so why simulate?

[snip]

So you've been converted to the Bob Pease school of hand waving ?

My POV: Design puts the idea onto paper. Simulation proves that what
is on the paper really works. But simulators don't "design". In my
business, simulation "proof" is required for each and every process
corner, otherwise the customer doesn't "buy".

...Jim Thompson

Your Sysreset sets Q high, but your sim starts with Q low. Why?

John

The default set-ups included FF initial conditions Q=0. If I uncheck
that box it starts, as would be expected, with Q=1.

...Jim Thompson

Well, run that. It's more interesting.

John

 

[Jim Thompson]

On Sat, 10 Nov 2007 14:40:51 -0700, Jim Thompson

On Sat, 10 Nov 2007 11:42:31 -0800, John Larkin

On Sat, 10 Nov 2007 11:57:19 -0700, Jim Thompson

[snip]

Now please present us with your "solution" with component names and
values and I'll simulate it side-by-side with my design.


I rarely simulate. Design is the reverse of simulation. Design forces
the desired results, so why simulate?

[snip]

So you've been converted to the Bob Pease school of hand waving ?

My POV: Design puts the idea onto paper. Simulation proves that what
is on the paper really works. But simulators don't "design". In my
business, simulation "proof" is required for each and every process
corner, otherwise the customer doesn't "buy".

...Jim Thompson


Your Sysreset sets Q high, but your sim starts with Q low. Why?

John

The default set-ups included FF initial conditions Q=0. If I uncheck
that box it starts, as would be expected, with Q=1.

...Jim Thompson

Well, run that. It's more interesting.

John

Yep. It takes one cycle for the output to be correct.

...Jim Thompson

 

[John Larkin]

On Sat, 10 Nov 2007 15:02:17 -0800, John Larkin

On Sat, 10 Nov 2007 14:40:51 -0700, Jim Thompson

On Sat, 10 Nov 2007 11:42:31 -0800, John Larkin

On Sat, 10 Nov 2007 11:57:19 -0700, Jim Thompson

[snip]

Now please present us with your "solution" with component names and
values and I'll simulate it side-by-side with my design.


I rarely simulate. Design is the reverse of simulation. Design forces
the desired results, so why simulate?

[snip]

So you've been converted to the Bob Pease school of hand waving ?

My POV: Design puts the idea onto paper. Simulation proves that what
is on the paper really works. But simulators don't "design". In my
business, simulation "proof" is required for each and every process
corner, otherwise the customer doesn't "buy".

...Jim Thompson


Your Sysreset sets Q high, but your sim starts with Q low. Why?

John


The default set-ups included FF initial conditions Q=0. If I uncheck
that box it starts, as would be expected, with Q=1.

...Jim Thompson

Well, run that. It's more interesting.

John

Yep. It takes one cycle for the output to be correct.

...Jim Thompson

It seems to work, but it's awfully convoluted. It would be, for me,
like one of those things that I designed but that I can barely
understand myself; there are too many possible states, and the dflop
clock sometimes comes from the input, and sometimes comes from the
input xored with the internal delay. And the input can chatter, or it
could be a single edge of either polarity. All those conditions have
to be proven to work, and proving it is too much work.

I avoid clever stuff like that, in hardware and in software. Sorry,
but I prefer my first circuit, because it's a lot easier to
understand.

John

 

[John Fields]

On Sat, 10 Nov 2007 11:57:19 -0700, Jim Thompson
[snip]

Now please present us with your "solution" with component names and
values and I'll simulate it side-by-side with my design.

I rarely simulate. Design is the reverse of simulation. Design forces
the desired results, so why simulate?

[snip]

So you've been converted to the Bob Pease school of hand waving ?

My POV: Design puts the idea onto paper. Simulation proves that what
is on the paper really works. But simulators don't "design". In my
business, simulation "proof" is required for each and every process
corner, otherwise the customer doesn't "buy".

---
I used to be in Larkin's corner, defending "build and test" over
"simulate", but after writing a few simulators to solve specific
problems posed here on sed, which couldn't be solved, practically,
any other way, I decided to lay down my wire-wrap gun until the
machine worked in the computer.

Then, along came wonderful, free LTSPICE.

I've designed stuff using it which I never had to physically build,
but which worked and which I got paid for, which is a joy.

A feeling I'm sure you enjoyed before I did.

 

[D from BC]

Like you do on Usenet? ;-)

Yup....

I've been thinking about the posted schematics.
It's a little overwhelming..

Here's a rough model of a JL based cct. without the RC.
This was described by myself in a prior post. Jim also saw this
coming.

http://www.members.shaw.ca/chainsaw/SED/JLbasedcct.jpg
644Kb screen capture

I'm 'painting' now with another JL inspired design (the one with
the front end differentiator).
If all goes well ..
It's 2 devices from 2 IC's.
4.5nS of prop delay.
Good timing behavior such as no lock up and fast initialization.
Operates with a wide range of pulse widths with f=0 to f=circuit
limit.

Will post soon it's not too gibberish


D from BC

 

[D from BC]

On Sat, 10 Nov 2007 11:57:19 -0700, Jim Thompson
[snip]

Now please present us with your "solution" with component names and
values and I'll simulate it side-by-side with my design.


I rarely simulate. Design is the reverse of simulation. Design forces
the desired results, so why simulate?

[snip]

So you've been converted to the Bob Pease school of hand waving ?

My POV: Design puts the idea onto paper. Simulation proves that what
is on the paper really works. But simulators don't "design". In my
business, simulation "proof" is required for each and every process
corner, otherwise the customer doesn't "buy".

---
I used to be in Larkin's corner, defending "build and test" over
"simulate", but after writing a few simulators to solve specific
problems posed here on sed, which couldn't be solved, practically,
any other way, I decided to lay down my wire-wrap gun until the
machine worked in the computer.

Then, along came wonderful, free LTSPICE.

I've designed stuff using it which I never had to physically build,
but which worked and which I got paid for, which is a joy.

A feeling I'm sure you enjoyed before I did.

I still find it amazing that after benchtesting, I can see that I
forgot to include parasitics in a circuit model.
After including the parasitics in the model, I get the sim waveforms
that I see on the scope

Bouncing between model and bench and model and bench can build a good
model.


D from BC

 

[ChairmanOfTheBored]

On Sat, 10 Nov 2007 11:42:31 -0800, John Larkin

On Sat, 10 Nov 2007 11:57:19 -0700, Jim Thompson

[snip]

Now please present us with your "solution" with component names and
values and I'll simulate it side-by-side with my design.


I rarely simulate. Design is the reverse of simulation. Design forces
the desired results, so why simulate?

[snip]

So you've been converted to the Bob Pease school of hand waving ?

My POV: Design puts the idea onto paper. Simulation proves that what
is on the paper really works. But simulators don't "design". In my
business, simulation "proof" is required for each and every process
corner, otherwise the customer doesn't "buy".

---
I used to be in Larkin's corner, defending "build and test" over
"simulate", but after writing a few simulators to solve specific
problems posed here on sed, which couldn't be solved, practically,
any other way, I decided to lay down my wire-wrap gun until the
machine worked in the computer.

Then, along came wonderful, free LTSPICE.

I've designed stuff using it which I never had to physically build,
but which worked and which I got paid for, which is a joy.

A feeling I'm sure you enjoyed before I did.

I still find it amazing that after benchtesting, I can see that I
forgot to include parasitics in a circuit model.
After including the parasitics in the model, I get the sim waveforms
that I see on the scope

Bouncing between model and bench and model and bench can build a good
model.

Forgetting the parasitic aspects of circuit configurations as well as
the individual components themselves is the main reason why those that do
not like simulators hate to use them. They fail at doing so.

A good sim will match the real circuit just about exactly. Considering
the elements of the software used to make a sim a sim, it would have to.

It's like Ohm's Law. The rules are the rules, and if you are following
them, your calculator will display the proper figure in its mantissa.

Sims work great. I love 'em. When they don't match the real data
gathered, and the engineer goes about the chore of finding out why, he
should also increase his education in the field as a result. A proper
sim will always match the real data. If it doesn't, something was left
out. It is like a puzzle.

 

[John Fields]

On Sat, 10 Nov 2007 11:42:31 -0800, John Larkin

On Sat, 10 Nov 2007 11:57:19 -0700, Jim Thompson

[snip]

Now please present us with your "solution" with component names and
values and I'll simulate it side-by-side with my design.


I rarely simulate. Design is the reverse of simulation. Design forces
the desired results, so why simulate?

[snip]

So you've been converted to the Bob Pease school of hand waving ?

My POV: Design puts the idea onto paper. Simulation proves that what
is on the paper really works. But simulators don't "design". In my
business, simulation "proof" is required for each and every process
corner, otherwise the customer doesn't "buy".

---
I used to be in Larkin's corner, defending "build and test" over
"simulate", but after writing a few simulators to solve specific
problems posed here on sed, which couldn't be solved, practically,
any other way, I decided to lay down my wire-wrap gun until the
machine worked in the computer.

Then, along came wonderful, free LTSPICE.

I've designed stuff using it which I never had to physically build,
but which worked and which I got paid for, which is a joy.

A feeling I'm sure you enjoyed before I did.

I still find it amazing that after benchtesting, I can see that I
forgot to include parasitics in a circuit model.
After including the parasitics in the model, I get the sim waveforms
that I see on the scope

Bouncing between model and bench and model and bench can build a good
model.

 

[John Larkin]

On Sat, 10 Nov 2007 11:57:19 -0700, Jim Thompson
[snip]

Now please present us with your "solution" with component names and
values and I'll simulate it side-by-side with my design.


I rarely simulate. Design is the reverse of simulation. Design forces
the desired results, so why simulate?

[snip]

So you've been converted to the Bob Pease school of hand waving ?

My POV: Design puts the idea onto paper. Simulation proves that what
is on the paper really works. But simulators don't "design". In my
business, simulation "proof" is required for each and every process
corner, otherwise the customer doesn't "buy".

---
I used to be in Larkin's corner, defending "build and test" over
"simulate", but after writing a few simulators to solve specific
problems posed here on sed, which couldn't be solved, practically,
any other way, I decided to lay down my wire-wrap gun until the
machine worked in the computer.

Then, along came wonderful, free LTSPICE.

I've designed stuff using it which I never had to physically build,
but which worked and which I got paid for, which is a joy.

A feeling I'm sure you enjoyed before I did.

An asynchronous circuit like this, and even moreso some of the others
that gave been posted, has internal delays and is subject to all
possible timings in the chatter zone. Spice can't really test all the
possible combinations of timings. You can generate a chatter
simulator, but you can't be sure its deterministic behavior represents
the real world of arbitrary timings. Complex async circuits can have
low-probability picosecond-wide windows of hazard.

John

 

[D from BC]

On Sat, 10 Nov 2007 11:42:31 -0800, John Larkin

On Sat, 10 Nov 2007 11:57:19 -0700, Jim Thompson

[snip]

Now please present us with your "solution" with component names and
values and I'll simulate it side-by-side with my design.


I rarely simulate. Design is the reverse of simulation. Design forces
the desired results, so why simulate?

[snip]

So you've been converted to the Bob Pease school of hand waving ?

My POV: Design puts the idea onto paper. Simulation proves that what
is on the paper really works. But simulators don't "design". In my
business, simulation "proof" is required for each and every process
corner, otherwise the customer doesn't "buy".

---
I used to be in Larkin's corner, defending "build and test" over
"simulate", but after writing a few simulators to solve specific
problems posed here on sed, which couldn't be solved, practically,
any other way, I decided to lay down my wire-wrap gun until the
machine worked in the computer.

Then, along came wonderful, free LTSPICE.

I've designed stuff using it which I never had to physically build,
but which worked and which I got paid for, which is a joy.

A feeling I'm sure you enjoyed before I did.

An asynchronous circuit like this, and even moreso some of the others
that gave been posted, has internal delays and is subject to all
possible timings in the chatter zone. Spice can't really test all the
possible combinations of timings. You can generate a chatter
simulator, but you can't be sure its deterministic behavior represents
the real world of arbitrary timings. Complex async circuits can have
low-probability picosecond-wide windows of hazard.

John

You've posted the hazards of asynch..ummmm..I'd say 5x.
Now that persistence.


D from BC

 

[D from BC]

On Sat, 10 Nov 2007 11:42:31 -0800, John Larkin

On Sat, 10 Nov 2007 11:57:19 -0700, Jim Thompson

[snip]

Now please present us with your "solution" with component names and
values and I'll simulate it side-by-side with my design.


I rarely simulate. Design is the reverse of simulation. Design forces
the desired results, so why simulate?

[snip]

So you've been converted to the Bob Pease school of hand waving ?

My POV: Design puts the idea onto paper. Simulation proves that what
is on the paper really works. But simulators don't "design". In my
business, simulation "proof" is required for each and every process
corner, otherwise the customer doesn't "buy".

---
I used to be in Larkin's corner, defending "build and test" over
"simulate", but after writing a few simulators to solve specific
problems posed here on sed, which couldn't be solved, practically,
any other way, I decided to lay down my wire-wrap gun until the
machine worked in the computer.

Then, along came wonderful, free LTSPICE.

I've designed stuff using it which I never had to physically build,
but which worked and which I got paid for, which is a joy.

A feeling I'm sure you enjoyed before I did.

An asynchronous circuit like this, and even moreso some of the others
that gave been posted, has internal delays and is subject to all
possible timings in the chatter zone. Spice can't really test all the
possible combinations of timings. You can generate a chatter
simulator, but you can't be sure its deterministic behavior represents
the real world of arbitrary timings. Complex async circuits can have
low-probability picosecond-wide windows of hazard.

John

I got inspired by that differentiator + schmitt invertor sketch of
yours.
The idea was to move the signal into the hysteresis levels.
I though I'd try doing the opposite..Moving the hystersis levels to
meet the signal..

Check out my hysteretic hairball! :O *
http://www.members.shaw.ca/chainsaw/SED/compsolution.jpg
569Kb

Notes:
* Top wave is the inverting input of U1.
(It's a cool waveform. 4 levels! )
* Prop delay is from a single device at less than 10nS.
* This can be a 1 chip solution with a fast dual comparator.
* I picked the LT1713 just because it's fast.
* The integrator + U2 could be replaced by some 'one shot' IC solution
* This circuit is not quite baked because I skipped on the math and
did best guesses on the resistor values.

With some tweaking, I think this might be a good circuit.

D from BC

 

[John Fields]

On Sat, 10 Nov 2007 19:55:00 -0600, John Fields


An asynchronous circuit like this, and even moreso some of the others
that gave been posted, has internal delays and is subject to all
possible timings in the chatter zone.

---
Oh my, how awful!
---

Spice can't really test all the
possible combinations of timings.