Debouncing....at About 1Mhz

[Jim Thompson]

On Sat, 10 Nov 2007 16:19:54 -0800, John Larkin
[snip]

Your Sysreset sets Q high, but your sim starts with Q low. Why?

John


The default set-ups included FF initial conditions Q=0. If I uncheck
that box it starts, as would be expected, with Q=1.

...Jim Thompson

Well, run that. It's more interesting.

John

Yep. It takes one cycle for the output to be correct.

...Jim Thompson

It seems to work, but it's awfully convoluted. It would be, for me,
like one of those things that I designed but that I can barely
understand myself; there are too many possible states, and the dflop
clock sometimes comes from the input, and sometimes comes from the
input xored with the internal delay.

Think of the XOR as a device that is switched from being an inverter
to being a buffer. The switching does not occur while clock (input)
edges are present.

And the input can chatter, or it

Does nothing after the first transition... it's an edge-triggered
flop.

could be a single edge of either polarity. All those conditions have
to be proven to work, and proving it is too much work.

I avoid clever stuff like that, in hardware and in software. Sorry,
but I prefer my first circuit, because it's a lot easier to
understand.

John

When I feel confused I drinks a glass of wine ;-)

...Jim Thompson

 

[Jim Thompson]

On Sat, 10 Nov 2007 11:57:19 -0700, Jim Thompson
[snip]

Now please present us with your "solution" with component names and
values and I'll simulate it side-by-side with my design.


I rarely simulate. Design is the reverse of simulation. Design forces
the desired results, so why simulate?

[snip]

So you've been converted to the Bob Pease school of hand waving ?

My POV: Design puts the idea onto paper. Simulation proves that what
is on the paper really works. But simulators don't "design". In my
business, simulation "proof" is required for each and every process
corner, otherwise the customer doesn't "buy".

---
I used to be in Larkin's corner, defending "build and test" over
"simulate", but after writing a few simulators to solve specific
problems posed here on sed, which couldn't be solved, practically,
any other way, I decided to lay down my wire-wrap gun until the
machine worked in the computer.

Then, along came wonderful, free LTSPICE.

I've designed stuff using it which I never had to physically build,
but which worked and which I got paid for, which is a joy.

A feeling I'm sure you enjoyed before I did.

It took me MANY years to trust simulators. Initially even bipolar
device models were bad.

But I still "design" by first "sketching", even if the "sketching"
does use a schematic capture program... I'm faster that way, no
erasing... drag stuff around... such fun!

Then I simulate.

...Jim Thompson

 

[John Larkin]

On Sat, 10 Nov 2007 16:19:54 -0800, John Larkin
[snip]

Your Sysreset sets Q high, but your sim starts with Q low. Why?

John


The default set-ups included FF initial conditions Q=0. If I uncheck
that box it starts, as would be expected, with Q=1.

...Jim Thompson

Well, run that. It's more interesting.

John

Yep. It takes one cycle for the output to be correct.

...Jim Thompson

It seems to work, but it's awfully convoluted. It would be, for me,
like one of those things that I designed but that I can barely
understand myself; there are too many possible states, and the dflop
clock sometimes comes from the input, and sometimes comes from the
input xored with the internal delay.

Think of the XOR as a device that is switched from being an inverter
to being a buffer. The switching does not occur while clock (input)
edges are present.

And the input can chatter, or it

Does nothing after the first transition... it's an edge-triggered
flop.

could be a single edge of either polarity. All those conditions have
to be proven to work, and proving it is too much work.

I avoid clever stuff like that, in hardware and in software. Sorry,
but I prefer my first circuit, because it's a lot easier to
understand.

John

When I feel confused I drinks a glass of wine ;-)

...Jim Thompson

One of the great engineering virtues is laziness. I consider a circuit
or a piece of code or a mechanism and say "that's going to be way too
much work" so I put it off for a while, or talk to somebody about it.
Usually something simpler emerges. Too many people, cursed with excess
energy, just plow ahead and implement the first idea they have. And
when it turns out to have bugs, as complex things will, they add stuff
to repair the bugs.

John

 

[John Larkin]

On Sat, 10 Nov 2007 14:40:51 -0700, Jim Thompson

On Sat, 10 Nov 2007 11:42:31 -0800, John Larkin

On Sat, 10 Nov 2007 11:57:19 -0700, Jim Thompson

[snip]

Now please present us with your "solution" with component names and
values and I'll simulate it side-by-side with my design.


I rarely simulate. Design is the reverse of simulation. Design forces
the desired results, so why simulate?

[snip]

So you've been converted to the Bob Pease school of hand waving ?

My POV: Design puts the idea onto paper. Simulation proves that what
is on the paper really works. But simulators don't "design". In my
business, simulation "proof" is required for each and every process
corner, otherwise the customer doesn't "buy".

---
I used to be in Larkin's corner, defending "build and test" over
"simulate", but after writing a few simulators to solve specific
problems posed here on sed, which couldn't be solved, practically,
any other way, I decided to lay down my wire-wrap gun until the
machine worked in the computer.

Then, along came wonderful, free LTSPICE.

I've designed stuff using it which I never had to physically build,
but which worked and which I got paid for, which is a joy.

A feeling I'm sure you enjoyed before I did.

An asynchronous circuit like this, and even moreso some of the others
that gave been posted, has internal delays and is subject to all
possible timings in the chatter zone. Spice can't really test all the
possible combinations of timings. You can generate a chatter
simulator, but you can't be sure its deterministic behavior represents
the real world of arbitrary timings. Complex async circuits can have
low-probability picosecond-wide windows of hazard.

John

I got inspired by that differentiator + schmitt invertor sketch of
yours.
The idea was to move the signal into the hysteresis levels.
I though I'd try doing the opposite..Moving the hystersis levels to
meet the signal..

Check out my hysteretic hairball! :O *
http://www.members.shaw.ca/chainsaw/SED/compsolution.jpg
569Kb

Yeah, I was thinking along those lines. This is a "feed-beside" sort
of concept, a brutally fast forward path, with slower tweaks off to
the side to fix the low-speed defects. This was the concept Tek used
in their 7000 series oscilloscopes.

I was also thinking that the origical hysteresis idea was OK except
that the hyst band of cmos schmitts is poorly defined. That's fixable
by defining it better, namely by adding additional hysteresis. The
numbers ought to work.

John

 

[John Larkin]

OK, design buggy stuff if that's what you enjoy.

John

 

[Jim Thompson]

On Sat, 10 Nov 2007 16:19:54 -0800, John Larkin
[snip]

Your Sysreset sets Q high, but your sim starts with Q low. Why?

John


The default set-ups included FF initial conditions Q=0. If I uncheck
that box it starts, as would be expected, with Q=1.

...Jim Thompson

Well, run that. It's more interesting.

John

Yep. It takes one cycle for the output to be correct.

...Jim Thompson

It seems to work, but it's awfully convoluted. It would be, for me,
like one of those things that I designed but that I can barely
understand myself; there are too many possible states, and the dflop
clock sometimes comes from the input, and sometimes comes from the
input xored with the internal delay.

Think of the XOR as a device that is switched from being an inverter
to being a buffer. The switching does not occur while clock (input)
edges are present.

And the input can chatter, or it

Does nothing after the first transition... it's an edge-triggered
flop.

could be a single edge of either polarity. All those conditions have
to be proven to work, and proving it is too much work.

I avoid clever stuff like that, in hardware and in software. Sorry,
but I prefer my first circuit, because it's a lot easier to
understand.

John

When I feel confused I drinks a glass of wine ;-)

...Jim Thompson

With PREbar functional....

http://www.analog-innovations.com/SED/AlternatingEdge-Unobtanium.pdf

I use that inverter/buffer characteristic of the XOR a lot...

Say I have an 8GHz (Johnson-type) divider chain down to 125MHz...
object to create single-side-band. (Mixed-mode to boot... CML down to
around 500MHZ, then CMOS.)

Since it's a Johnson counter with no set or reset, how do I guarantee
the phase relationship of the 8GHz to the 125MHz?

Answer, I don't.

What I did was measure literally, using a cell aptly named
"WhosOnFirst.sch" (*) and invert as needed.

(*) No one got the joke. Youngsters :-(

...Jim Thompson

 

[Jim Thompson]

On Sun, 11 Nov 2007 08:25:59 -0700, Jim Thompson
[snip]

When I feel confused I drinks a glass of wine ;-)

...Jim Thompson

One of the great engineering virtues is laziness. I consider a circuit
or a piece of code or a mechanism and say "that's going to be way too
much work" so I put it off for a while, or talk to somebody about it.
Usually something simpler emerges. Too many people, cursed with excess
energy, just plow ahead and implement the first idea they have. And
when it turns out to have bugs, as complex things will, they add stuff
to repair the bugs.

John

I've been known to toss designs that I had been working for
weeks/months, because of too many "patches".

Panics the hell out of clients until they see the results of a clean
start.

...Jim Thompson

 

[John Larkin]

On Sun, 11 Nov 2007 08:25:59 -0700, Jim Thompson
[snip]

When I feel confused I drinks a glass of wine ;-)

...Jim Thompson

One of the great engineering virtues is laziness. I consider a circuit
or a piece of code or a mechanism and say "that's going to be way too
much work" so I put it off for a while, or talk to somebody about it.
Usually something simpler emerges. Too many people, cursed with excess
energy, just plow ahead and implement the first idea they have. And
when it turns out to have bugs, as complex things will, they add stuff
to repair the bugs.

John

I've been known to toss designs that I had been working for
weeks/months, because of too many "patches".

Panics the hell out of clients until they see the results of a clean
start.

...Jim Thompson

It takes guts to dump something you've put three months into. Even if
the new thing would be better and finished sooner. It's even more
difficult in a team design, where peer pressure exists. But yeah, I'll
consider dumping a design that's far along, even finished, when a
better or simpler idea pops up, or when the original starts creaking
of its own weight.

That's why it's better to not start too soon, to play with ideas for a
while at the start.

John

 

[John Larkin]

On Sat, 10 Nov 2007 18:03:07 -0700, Jim Thompson

On Sat, 10 Nov 2007 16:19:54 -0800, John Larkin
[snip]

Your Sysreset sets Q high, but your sim starts with Q low. Why?

John


The default set-ups included FF initial conditions Q=0. If I uncheck
that box it starts, as would be expected, with Q=1.

...Jim Thompson

Well, run that. It's more interesting.

John

Yep. It takes one cycle for the output to be correct.

...Jim Thompson


It seems to work, but it's awfully convoluted. It would be, for me,
like one of those things that I designed but that I can barely
understand myself; there are too many possible states, and the dflop
clock sometimes comes from the input, and sometimes comes from the
input xored with the internal delay.

Think of the XOR as a device that is switched from being an inverter
to being a buffer. The switching does not occur while clock (input)
edges are present.

And the input can chatter, or it

Does nothing after the first transition... it's an edge-triggered
flop.

could be a single edge of either polarity. All those conditions have
to be proven to work, and proving it is too much work.

I avoid clever stuff like that, in hardware and in software. Sorry,
but I prefer my first circuit, because it's a lot easier to
understand.

John

When I feel confused I drinks a glass of wine ;-)

...Jim Thompson

With PREbar functional....

http://www.analog-innovations.com/SED/AlternatingEdge-Unobtanium.pdf

I use that inverter/buffer characteristic of the XOR a lot...

Say I have an 8GHz (Johnson-type) divider chain down to 125MHz...
object to create single-side-band. (Mixed-mode to boot... CML down to
around 500MHZ, then CMOS.)

Since it's a Johnson counter with no set or reset, how do I guarantee
the phase relationship of the 8GHz to the 125MHz?

Answer, I don't.

What I did was measure literally, using a cell aptly named
"WhosOnFirst.sch" (*) and invert as needed.

(*) No one got the joke. Youngsters :-(

...Jim Thompson

I've done that in Manchester-coded optical systems. If the uP doesn't
see good data frames for a while, it sets a bit to xor the data
stream, and sets another bit to open up the pll filter bandwidth.

John

 

[Jim Thompson]

On Sun, 11 Nov 2007 09:05:43 -0700, Jim Thompson
[snip]

I've been known to toss designs that I had been working for
weeks/months, because of too many "patches".

Panics the hell out of clients until they see the results of a clean
start.

...Jim Thompson

It takes guts to dump something you've put three months into. Even if
the new thing would be better and finished sooner. It's even more
difficult in a team design, where peer pressure exists. But yeah, I'll
consider dumping a design that's far along, even finished, when a
better or simpler idea pops up, or when the original starts creaking
of its own weight.

That's why it's better to not start too soon, to play with ideas for a
while at the start.

John

My wife says I have the Michelangelo syndrome, with the Pope (aka the
client) saying, "When will you make an end?"

I'm always striving for that simple perfect work of art ;-)

...Jim Thompson

 

[Michael A. Terrell]

What I did was measure literally, using a cell aptly named
"WhosOnFirst.sch" (*) and invert as needed.

http://www.baseball-almanac.com/humor4.shtml


--
Service to my country? Been there, Done that, and I've got my DD214 to
prove it.
Member of DAV #85.

Michael A. Terrell
Central Florida

 

[Michael A. Terrell]

On Sat, 10 Nov 2007 11:42:31 -0800, John Larkin

On Sat, 10 Nov 2007 11:57:19 -0700, Jim Thompson

[snip]

Now please present us with your "solution" with component names and
values and I'll simulate it side-by-side with my design.


I rarely simulate. Design is the reverse of simulation. Design forces
the desired results, so why simulate?

[snip]

So you've been converted to the Bob Pease school of hand waving ?

My POV: Design puts the idea onto paper. Simulation proves that what
is on the paper really works. But simulators don't "design". In my
business, simulation "proof" is required for each and every process
corner, otherwise the customer doesn't "buy".

---
I used to be in Larkin's corner, defending "build and test" over
"simulate", but after writing a few simulators to solve specific
problems posed here on sed, which couldn't be solved, practically,
any other way, I decided to lay down my wire-wrap gun until the
machine worked in the computer.

Then, along came wonderful, free LTSPICE.

I've designed stuff using it which I never had to physically build,
but which worked and which I got paid for, which is a joy.

A feeling I'm sure you enjoyed before I did.

It took me MANY years to trust simulators. Initially even bipolar
device models were bad.

But I still "design" by first "sketching", even if the "sketching"
does use a schematic capture program... I'm faster that way, no
erasing... drag stuff around... such fun!

You don't drag them, you push them around! ;-)


--
Service to my country? Been there, Done that, and I've got my DD214 to
prove it.
Member of DAV #85.

Michael A. Terrell
Central Florida

 

[John Larkin]

On Sat, 10 Nov 2007 18:03:07 -0700, Jim Thompson

On Sat, 10 Nov 2007 16:19:54 -0800, John Larkin
[snip]

Your Sysreset sets Q high, but your sim starts with Q low. Why?

John


The default set-ups included FF initial conditions Q=0. If I uncheck
that box it starts, as would be expected, with Q=1.

...Jim Thompson

Well, run that. It's more interesting.

John

Yep. It takes one cycle for the output to be correct.

...Jim Thompson


It seems to work, but it's awfully convoluted. It would be, for me,
like one of those things that I designed but that I can barely
understand myself; there are too many possible states, and the dflop
clock sometimes comes from the input, and sometimes comes from the
input xored with the internal delay.

Think of the XOR as a device that is switched from being an inverter
to being a buffer. The switching does not occur while clock (input)
edges are present.

And the input can chatter, or it

Does nothing after the first transition... it's an edge-triggered
flop.

could be a single edge of either polarity. All those conditions have
to be proven to work, and proving it is too much work.

I avoid clever stuff like that, in hardware and in software. Sorry,
but I prefer my first circuit, because it's a lot easier to
understand.

John

When I feel confused I drinks a glass of wine ;-)

...Jim Thompson

With PREbar functional....

http://www.analog-innovations.com/SED/AlternatingEdge-Unobtanium.pdf

I use that inverter/buffer characteristic of the XOR a lot...

Say I have an 8GHz (Johnson-type) divider chain down to 125MHz...
object to create single-side-band. (Mixed-mode to boot... CML down to
around 500MHZ, then CMOS.)

Since it's a Johnson counter with no set or reset, how do I guarantee
the phase relationship of the 8GHz to the 125MHz?

Answer, I don't.

What I did was measure literally, using a cell aptly named
"WhosOnFirst.sch" (*) and invert as needed.

(*) No one got the joke. Youngsters :-(

...Jim Thompson

At the peak of the Beatles era, I designed the "Come Together" circuit
for levelling the steam pressures from two boilers that had separate
control loops.

Did you like my Seesaw Inverter?

John

 

[John Fields]

On Sun, 11 Nov 2007 01:32:07 -0800, D from BC


Yeah, I was thinking along those lines. This is a "feed-beside" sort
of concept, a brutally fast forward path, with slower tweaks off to
the side to fix the low-speed defects. This was the concept Tek used
in their 7000 series oscilloscopes.

I was also thinking that the origical hysteresis idea was OK except
that the hyst band of cmos schmitts is poorly defined. That's fixable
by defining it better, namely by adding additional hysteresis. The
numbers ought to work.

---
I think this pretty much takes care of it all.

Version 4
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TEXT -112 256 Left 0 !.tran 10e-6 uic
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[D from BC]

On Sat, 10 Nov 2007 11:42:31 -0800, John Larkin

On Sat, 10 Nov 2007 11:57:19 -0700, Jim Thompson

[snip]

Now please present us with your "solution" with component names and
values and I'll simulate it side-by-side with my design.


I rarely simulate. Design is the reverse of simulation. Design forces
the desired results, so why simulate?

[snip]

So you've been converted to the Bob Pease school of hand waving ?

My POV: Design puts the idea onto paper. Simulation proves that what
is on the paper really works. But simulators don't "design". In my
business, simulation "proof" is required for each and every process
corner, otherwise the customer doesn't "buy".

---
I used to be in Larkin's corner, defending "build and test" over
"simulate", but after writing a few simulators to solve specific
problems posed here on sed, which couldn't be solved, practically,
any other way, I decided to lay down my wire-wrap gun until the
machine worked in the computer.

Then, along came wonderful, free LTSPICE.

I've designed stuff using it which I never had to physically build,
but which worked and which I got paid for, which is a joy.

A feeling I'm sure you enjoyed before I did.

It took me MANY years to trust simulators. Initially even bipolar
device models were bad.

But I still "design" by first "sketching", even if the "sketching"
does use a schematic capture program... I'm faster that way, no
erasing... drag stuff around... such fun!

Then I simulate.

...Jim Thompson

I still sketch for the tough problems.
That gives me the freedom to express the problem in any fashion.
If drawing cartoons of a little choo choo train stuck in a valley
helps to solve the circuit ... great!

Also, I think I can move my pen faster than a mouse.
D from BC

 

[John Larkin]

Think of the XOR as a device that is switched from being an inverter
to being a buffer. The switching does not occur while clock (input)
edges are present.


Does nothing after the first transition... it's an edge-triggered
flop.


When I feel confused I drinks a glass of wine ;-)

...Jim Thompson

Coffee works better for me.

OK, how about this?

http://img225.imageshack.us/my.php?image=catchernv0.jpg


John

 

[D from BC]

[snipped .asc file for less scrolling]

Yup ..this is in the same solution family.

Without running a sim, I can see how this works..
It's comparator reference level shifting by differentiator.
The differentiator pops the - input into oblivion for a time which
makes the comparator dead and that's how the fuzzy edges are skipped.
Nice....
Uses single output op amps.
Single device prop delay.
1 IC solution.
Fast.

I like my 80% baked solution on
http://www.members.shaw.ca/chainsaw/SED/compsolution.jpg

The first op amp is unstable. When an edge crosses the threshold the
comparator locks up fast due to a local positive feedback loop.
The input signal probably can't compete with this and therefore no
race condition exists and it's unlikely the timing will fault.
(Yes...I got scared by JL posts of asynch hairballs. )

JF, I see a 2 comparator delay in disabling the first comparator.
I have to wonder if some glitch could still slip through..

In my circuit the first comparator is disabled by 1 comparator delay.


D from BC

 

[John Larkin]

Looks pretty good. The only hazard I can see is that a very fast spike
can blow through the first comparator before the second one has time
to come back around. That's a hazard with most all comparators that
have external hysteresis.

That's only a problem if the input can in fact have such fast spikes,
which in this case maybe it can't.

John

 

[D from BC]

On Sat, 10 Nov 2007 19:55:00 -0600, John Fields

On Sat, 10 Nov 2007 14:40:51 -0700, Jim Thompson

On Sat, 10 Nov 2007 11:42:31 -0800, John Larkin

On Sat, 10 Nov 2007 11:57:19 -0700, Jim Thompson

[snip]

Now please present us with your "solution" with component names and
values and I'll simulate it side-by-side with my design.


I rarely simulate. Design is the reverse of simulation. Design forces
the desired results, so why simulate?

[snip]

So you've been converted to the Bob Pease school of hand waving ?

My POV: Design puts the idea onto paper. Simulation proves that what
is on the paper really works. But simulators don't "design". In my
business, simulation "proof" is required for each and every process
corner, otherwise the customer doesn't "buy".

---
I used to be in Larkin's corner, defending "build and test" over
"simulate", but after writing a few simulators to solve specific
problems posed here on sed, which couldn't be solved, practically,
any other way, I decided to lay down my wire-wrap gun until the
machine worked in the computer.

Then, along came wonderful, free LTSPICE.

I've designed stuff using it which I never had to physically build,
but which worked and which I got paid for, which is a joy.

A feeling I'm sure you enjoyed before I did.

An asynchronous circuit like this, and even moreso some of the others
that gave been posted, has internal delays and is subject to all
possible timings in the chatter zone. Spice can't really test all the
possible combinations of timings. You can generate a chatter
simulator, but you can't be sure its deterministic behavior represents
the real world of arbitrary timings. Complex async circuits can have
low-probability picosecond-wide windows of hazard.

John

I got inspired by that differentiator + schmitt invertor sketch of
yours.
The idea was to move the signal into the hysteresis levels.
I though I'd try doing the opposite..Moving the hystersis levels to
meet the signal..

Check out my hysteretic hairball! :O *
http://www.members.shaw.ca/chainsaw/SED/compsolution.jpg
569Kb

Yeah, I was thinking along those lines. This is a "feed-beside" sort
of concept, a brutally fast forward path, with slower tweaks off to
the side to fix the low-speed defects. This was the concept Tek used
in their 7000 series oscilloscopes.

I was also thinking that the origical hysteresis idea was OK except
that the hyst band of cmos schmitts is poorly defined. That's fixable
by defining it better, namely by adding additional hysteresis. The
numbers ought to work.

John

Damn...that's right...This is freakn scope trigger tech...
I didn't notice.
Bummer... I'm reinventing the wheel again.

Now I'm wondering if I could have cheated and looked up oscilloscope
trigger circuit patents to dodge a whole lot of dinking with gates, D
ff's and one shots.
There should be ooodles of trigger art since the invention of the
oscilloscope.

What to do.....
Use time sifting through mountains of patents
versus
use time designing from scratch..


D from BC

 

[Jim Thompson]

Coffee works better for me.

OK, how about this?

http://img225.imageshack.us/my.php?image=catchernv0.jpg


John

I found, at least with 74HC' stuff, that I needed to delay the clock
flip-over as well... looked like SUAH timing was violated.

...Jim Thompson