Transistor switch time

[@xi@g@me]

Hello all
Again, thanks for the tips on chosing tools for my hobby!

I'm still working on the ESP8266 chip, and learning with the MAX7219 IC to control digits. As the ESP8266 output are 3.3V and the MAX7219 needs TTL-level inputs (that is, more than 3.3V for the high signal), I had to find a way to level up the voltage (with the elements I have)

I decided to use a very simple circuit, with a NPN transistor (2N2222), a 7.5k resistor to the base, a pullup resistor of 33k (5V) at the collector, and emitter to ground. Of course the signal is reversed, but whatever I'll just need to configure SPI differently to output inversed signals from the ESP8266.

Problem is, the transistor is claimed to have a switch time of 20ns, which is way sufficient for a clock cycle of 1MHz, but my measurements show a different result:

(Blue is chip select, purple is connected to the collector of the transistor, and yellow is unused)
Horizontal step is set to 2ms, so we have here a switch time of around 3.5ms (until 3.8V is reached).

If I look at the 2N2222 datasheet (at least one that I found), I see this graph:

With a 7.5k resistor, I shall have a base current of 0.34mA, which shall allow a collector current of 33.4mA max (approx) according to Beta. I will have to change the base resistor to a way lower value? That will increase the collector current, but cost more energy to the system...
Here is was I get with a 7.5k resistor :

That's better, but...

Shall I invest into a level shifter board instead, like the ones we see on aliexpress?

 

[Nanren888]

Sorry, not quite keeping up.
If the base is falling, the transistor is turning off, rather than on, so if it is turning off quickly and I have not done the maths of 7.5k into the capacitance, but if that is fast, then the rise we see looks like the 33k driving the line to the chip. Is that line long, or has significant capacitance?
If you remove the line to the chip and just probe the collector, is it still slow?
.
There's a common level shifter (3-5) using just a FET. Most of the level shifter boards I've seen have multiple on the same board.

 

[AnalogKid]

If I look at the 2N2222 datasheet (at least one that I found), I see this graph:

If you look at the graph, you will see in the upper left corner the conditions for the plots: the ratio of the collector current to the base current is 10. At larger ratios, such as 100, the transistor will be much slower.

Also . . .

With a 7.5k resistor, I shall have a base current of 0.34mA, which shall allow a collector current of 33.4mA max (approx) according to Beta.

VERY approx.

A transistor's beta is nothing near constant. It varies with base current, collector current, collector-emitter voltage, temperature, barometric pressure (really), and just about everything else except the phase of the moon. This is why transistors are operated nowhere near their limit if possible. Start with the collector current, then calculate the base circuit such that the required gain is only 10 to 20.

ak

 

[Harald Kapp]

Most of the level shifter boards I've seen have multiple on the same board.

Look up e.g. "TXS0108E Logic Level Converter". Bidirectional, 8 channels on one module.

 

[Harald Kapp]

The rise time of the output signal is on the order of 2 ms. That is equivalent to a -3db corner frequency of 175 Hz. With R = 33 kΩ that means a capacitive load of C ~ 25 nF. Such a high capacitive load calls for an active totem-pole output that can actively drive the line high.

There seems to be another quirk that I cannot explain by the RC time constant: The output seems to react after a delay of ~ 1 ms. As if there were an additional time constant a the base of the transistor. A quick simulation of the circuit as I understand it shows no such delay:


Show us your circuit diagram, including any external loads (capacitances) that may be present and where your points of measurement are.

 

[crutschow]

Horizontal step is set to 2ms

According to the display, the oscilloscope is set to 2µs per division, not 2ms.

The turn-off delay you are seeing is the storage time delay that most general purpose BJTs exhibit.
A switching transistor, such as the 2N2369 will have a much shorter storage time.

Alternately, a small capacitor (e.g. 20pF) across the base input resistor will help remove the stored charge and reduce the delay time.

 

[Harald Kapp]

According to the display, the oscilloscope is set to 2µs per division, not 2ms.

Well spotted. That changes everything, incl. my calculations and simulations by a factor of 1000. My bad for not having inspected the screenshot thoroughly enough

 

[@xi@g@me]

Yes, I'm sorry, I meant 2µs per division (and thanks for the word "division", I didn't remember how it was named) indeed.
For now, the output of the inverter circuit is not plugged into anything but the oscilloscope.

I'll provide a Kicad schematic as soon as I'll be home tonight. If I understand well, I must chose resistances so the gain sits between 10 and 20. I do not need to reach the transistor's limit, just go fast enough to support the clock speed.

And yes sorry, that's a switch off of the transistor, I got mislead by the output signal.

 

[crutschow]

I must chose resistances so the gain sits between 10 and 20.

Are you talking about the overdrive needed to switch a BJT?

Below is the LTspice simulation of the 2N2222 for a 1MHz signal, with (red trace) and without (yellow trace) a base speedup capacitor.
As you can see the capacitor allows it to respond to the signal, but without it, it's not fast enough.

The signal source must have a relatively low impedance for this to work.

The actual circuit may require some tweaking of the values to get the desired response.

 

[@xi@g@me]

Sorry for being late, private life etc.

Here's a rapid schematic I made using KiCad:


I did a capture with no capacitor, and the Clock_reversed signal does not even have the time to start moving down asyour Out2 signal does... I'll try with a cap, after some documentation on how base speed-up caps work.

The rise time of the output signal is on the order of 2 ms. That is equivalent to a -3db corner frequency of 175 Hz. With R = 33 kΩ that means a capacitive load of C ~ 25 nF. Such a high capacitive load calls for an active totem-pole output that can actively drive the line high.

I don't even undestand what you intend to say here, too complex for my current knowledge of the topic I guess :S

 

[crutschow]

I don't even undestand what you intend to say here,

The the transistor output risetime is slow because of excess capacitive load on it's output.
Reducing the collector resistor value will help that (at the expensive of more transistor current when on).