Reversed biased LED (again.. sorry) Thinking out loud

[George Herold]

Hi guys, I hope this is the last time for the following reversed
biased LED as Spad thread. (We've got to do a newsletter then manual,
so I need to at least wave my hands at the details.) I should also
apologize as this is mostly just my ‘thinking out loud’ to the SED.
So again here's the circuit.

+------+
| |
(+) |
Vbias - LED
(-) ^
| |
| +-----opa314-->out
| | buffer
GND 100k
|
GND

Vbias is ~24V (device dependent)
When light is shinned at the LED I see pulses.
the number of which changes linearly with light intensity.


There are two details for me to understand.
First I've been thinking about the data in terms of 'breakdown
channels' in the LED.
I assume they are independent, though I can imagine that some samples
might have
overlapping channels.
As any one channel breaks down it starts to discharges the entire LED
capacitance. Also each channel has a different threshold voltage.
When the voltage across the LED falls below that threshold then the
breakdown stops.
Does this make sense geometrically? The depletion width is much less
than the square root of the area. (Is depletion width the right
term?)

The data for this model is manifold. First here's a 'scope
'histogram' of single photon events, 1 second persistence. ~5kHz count
rate.
http://bayimg.com/DamOLaAeG
with the trigger set down near ground.

I sent the same data into a comparator with adjustable reference
voltage and get a stair case type distribution of count rate vs
voltage.
(data posted on request)

If you trigger up high, then you just see one channel. The peak
height is approximately equal to the bias voltage minus some
'Vt' (threshold voltage). Here's a bunch of 'scope shots with
different bias volatges.
Vt =~23.1V

http://bayimg.com/EAmolAAeG
http://bayimg.com/eaMONAAeG
http://bayimg.com/eAmopaaeG
http://bayimg.com/FAMoAAaeG

I’m not sure how to explain why each channel has a different threshold
voltage.

The other thing I don’t understand is the turn on waveform. At low
bias voltage and for early times with higher bias voltage the turn on
looks linear with a slope that is related to the voltage peak... it
takes about 50 – 100ns to turn on. (See the data above.) Now what’s
weird is this turn on time seems to be independent of circuit
following the LED. It’s independent of the quenching resistor value
(100k ohm for the circuit shown) And also independent of the
capacitance to ground. The R and C loading of the LED has an effect
at later times and with higher bias voltages.
Here’s a screen shot where I added 12pF to ground in parallel with the
100k ohm resistor.
http://bayimg.com/JaMagaAeH
If I do the same with lower bias voltage then there is almost no
change in the waveform.
I was expecting a slower ramp. The opa134 opamp that is used as a
buffer has a input C of ~5pF.


Anyway thanks for reading and any thoughts are most welcome.

George H.

 

[miso]

Most LEDS have a very low reverse bias abs max. I've seen as bad as 3V,
though usually they spec 6v for operation in a matrix. (5VDC operation
plus margin.]

Under high reverse bias, you can get them to glow, but it is due to
impact ionization rather than normal LED light output.

So I assume this is for scientific interest and not a practical circuit.

 

[George Herold]

The constant rise time is probably diffusion-limited, as in photodiodes.
  The carriers have to diffuse in and out of the undepleted regions.

Hmm, OK that's interesting. I've been mostly trying to think about
what happens in the avalnche region. So I had this impression that
once the charge carriers reached the neutral (undepeleted) region
(where they are majority carriers) that their image charges appeared
on the contacts and there was not much time delay.
I did a little reading about diffuison in photodiodes (S. Donati
"Photodetectors" pgs 129,130). And all he said was that charge
carriers generated in the undeplected region would have to diffuse
out.

Say if there is some time delay getting charges out of the LED, could
I look for the same time delay getting charges into it? (Hit it with
a voltage/current step and see how long it takes till I see light.
(I'm not sure I have a fast enough PD... but hacking something would
be fun!)

The different breakdown voltages are probably due to what the local E
field is at the position of the defect causing the channel.  You have to
be able to reach ionization energy within one mean free path or
thereabouts, which sets a lower limit on the local E.

In a fully depleted junction, E depends on the line integral of the
doping density, but at lower bias voltages, the doping is shielded by
the free carriers.  I suspect that most of the defects are near the
junction, and of course it's hard to make undoped compound
semiconductors, because any stoichiometry error translates into some
huge doping density.  Thus the local E at the defect positions could
change pretty fast with bias.

Yeah this is a weird LED. 700 nm GaP (which should be green) but it's
heavy doped with Zn. The manufacturer has what looks like a similar
LED, 700nm GaP with a clear lens and a bit more light. But that one
doesn't break down till 125 Volts!

George H.

 

[George Herold]

Most LEDS have a very low reverse bias abs max. I've seen as bad as 3V,
though usually they spec 6v for operation in a matrix. (5VDC operation
plus margin.]

Under high reverse bias, you can get them to glow, but it is due to
impact ionization rather than normal LED light output.

So I assume this is for scientific interest and not a practical circuit.

Hi miso, Well this is a of scientific interest but (hopefully) will
help sell
our counter/ timer. (It will be a ~$200 box) The whole thing started
with a question on SEB about the 5V reverse voltage of LEDs. So I
went and tried one.... turns out you can revese bias to a lot more
than 5V. 25 volts is the lowest I've found with other voltages
between 50 and 120.

George H.

 

[miso]

Most LEDS have a very low reverse bias abs max. I've seen as bad as 3V,
though usually they spec 6v for operation in a matrix. (5VDC operation
plus margin.]

Under high reverse bias, you can get them to glow, but it is due to
impact ionization rather than normal LED light output.

So I assume this is for scientific interest and not a practical circuit.

Hi miso, Well this is a of scientific interest but (hopefully) will
help sell
our counter/ timer. (It will be a ~$200 box) The whole thing started
with a question on SEB about the 5V reverse voltage of LEDs. So I
went and tried one.... turns out you can revese bias to a lot more
than 5V. 25 volts is the lowest I've found with other voltages
between 50 and 120.

George H.

Well yes, you can put a lot of reverse bias on a LED, but there is no
guarantee there is no damage to the device or all devices will have the
same breakdown.

In the days when the LED reverse bias spec was 3V, I had a bit of a
quandary designing display driver chips since that does involve a 5V
reverse bias. The story I got from "I can't say" was if you ruined a LED
at 5V reserve bias, it would have problems at normal forward bias. That
is, the physics behind a failure at a low reverse bias meant the forward
operation would have problems as well. That was when I brought up that
the physics were different between forward and reverse. But since the
rest of the industry has been selling display drivers that did the same
thing, the discussion was moot. [I don't remotely consider myself a
semiconductor physics expert. I only know enough to be dangerous.]

I can say that any time I have caused a diode to fail during ESD
testing, it has always been in reverse bias. You get a large field
potential, and something pops at a weak spot in the crystal lattice.
Forward bias failures tend to be related to electromigration, somewhat
unintuitive since you would think the diode would be weaker than the
metal. [Metal hasn't been plain metal for a long time. The connection
layers themselves can have complicated physics.]

But impact ionization isn't exactly an unknown phenomena. It is quite
possible some LED manufacturers tweak the junction profiles to make
their parts less likely to fail under that condition. [Much like the
multi-step doping they do on drains in "regular" CMOS to reduce the
problem.]

I'm willing to bet if you could find the person in a semi that does the
"production test" on wafers, they would have a spec on how much reverse
bias they put on the LEDs during that part of testing. "Production test"
isn't a standardized term in the industry. It can be called "acceptance
test" for example. But basically when you are buying processed wafers
from a fab or simply getting wafers from your captive fab, the
individual devices are characterized on a test pattern. This is prior to
wafer testing the actual product. [I never worked where they made
discrete semis, so this step could be just part of product testing for
discretes.] The acceptance test generates reams (well if you actually
printed them) of data on a per wafer basis. Somewhere in that spec is
how much reverse bias the factory considers acceptable and the current
limit. This may not be tested in production. There are arguments as to
whether devices should be stressed under production testing or just at
this wafer acceptance level.

This is why I say you never know exactly how specs are assured on a
datasheet. You need intimate knowledge of the test flow. Note also that
on a complex process, the customer can be shipped devices that fail
acceptance testing IF a chain of responsible people deem the test as not
relevant. The most common situation is when a product doesn't use the
device that is failing the acceptance test. For example, the product is
done on a bicmos process, but the device in question doesn't use any
bipolar devices.

For a basic semiconductor, testing merely means that if the part does
not meet specifications, then the manufacturer will give you a new part.
Kind of lame, but when you have lawyers, stuff like that happens.

 

[George Herold]

Most LEDS have a very low reverse bias abs max. I've seen as bad as 3V,
though usually they spec 6v for operation in a matrix. (5VDC operation
plus margin.]
Under high reverse bias, you can get them to glow, but it is due to
impact ionization rather than normal LED light output.
So I assume this is for scientific interest and not a practical circuit.

Hi miso,  Well this is a of scientific interest but (hopefully) will
help sell
our counter/ timer. (It will be a ~$200 box) The whole thing started
with a question on SEB about the 5V reverse voltage of LEDs.  So I
went and tried one.... turns out you can revese bias to a lot more
than 5V.  25 volts is the lowest I've found with other voltages
between 50 and 120.

George H.

Well yes, you can put a lot of reverse bias on a LED, but there is no
guarantee there is no damage to the device or all devices will have the
same breakdown.

In the days when the LED reverse bias spec was 3V, I had a bit of a
quandary designing display driver chips since that does involve a 5V
reverse bias. The story I got from "I can't say" was if you ruined a LED
at 5V reserve bias, it would have problems at normal forward bias. That
is, the physics behind a failure at a low reverse bias meant the forward
operation would have problems as well. That was when I brought up that
the physics were different between forward and reverse. But since the
rest of the industry has been selling display drivers that did the same
thing, the discussion was moot. [I don't remotely consider myself a
semiconductor physics expert. I only know enough to be dangerous.]

Grin... I'm far from any expert. As a post doc I did some FIR-IR
spectroscopy of GaAs/Al hetero junction devices.

I can say that any time I have caused a diode to fail during ESD
testing, it has always been in reverse bias. You get a large field
potential, and something pops at a weak spot in the crystal lattice.
Forward bias failures tend to be related to electromigration, somewhat
unintuitive since you would think the diode would be weaker than the
metal. [Metal hasn't been plain metal for a long time. The connection
layers themselves can have complicated physics.]

Yeah, these LED's always have 100k in series
(well with a switch down to ~30k, if the resistance is too low the
avalanche takes longer to stop... heading to always on.)

But impact ionization isn't exactly an unknown phenomena. It is quite
possible some LED manufacturers tweak the junction profiles to make
their parts less likely to fail under that condition. [Much like the
multi-step doping they do on drains in "regular" CMOS to reduce the
problem.]

I'm willing to bet if you could find the person in a semi that does the
"production test" on wafers, they would have a spec on how much reverse
bias they put on the LEDs during that part of testing. "Production test"
isn't a standardized term in the industry. It can be called "acceptance
test" for example.

Yeah, I sent an email to purdy electronics in Sunnyvale.
Hey if anyone knows someone...
The LED is a AND114 from newark

http://www.newark.com/optoelectronics/114-r/led-red-t-1-3-4-5mm-5mcd-700nm/dp/01H9629

I'll send them something again after the newsletter is written.
We'll have to make a life time buy. maybe 5-10k... at ~$0.1 ea.
Would someone 'notice' a question with a kilobuck attached?


But basically when you are buying processed wafers

from a fab or simply getting wafers from your captive fab, the
individual devices are characterized on a test pattern. This is prior to
wafer testing the actual product. [I never worked where they made
discrete semis, so this step could be just part of product testing for
discretes.] The acceptance test generates reams (well if you actually
printed them) of data on a per wafer basis. Somewhere in that spec is
how much reverse bias the factory considers acceptable and the current
limit. This may not be tested in production. There are arguments as to
whether devices should be stressed under production testing or just at
this wafer acceptance level.

This is why I say you never know exactly how specs are assured on a
datasheet. You need intimate knowledge of the test flow. Note also that
on a complex process, the customer can be shipped devices that fail
acceptance testing IF a chain of responsible people deem the test as not
relevant. The most common situation is when a product doesn't use the
device that is failing the acceptance test. For example, the product is
done on a bicmos process, but the device in question doesn't use any
bipolar devices.

For a basic semiconductor, testing merely means that if the part does
not meet specifications, then the manufacturer will give you a new part.
Kind of lame, but when you have lawyers, stuff like that happens.- Hide quoted text -

- Show quoted text -

Thanks miso, most of the time I just feel like a pimple on a flea
sucking on some dog that is part of consumer electronics.
But I'm a happy pimple! life would stink w/o the dog.

 

[George Herold]

The slow turn-on of PIN rectifiers is another example of
diffusion-dominated conduction.

So where do you think the diffusion limited current might be
occurring?
(some transition region between netrual and depleted sections?)

I remember distinctly hooking up a x10 (16pF) scope probe to the non-
inverting node,
and the signal didn't change... well only a little.
(It's like the dog that didn't bark)

George H.

 

[miso]

I guess I wasn't too clear about the wafer acceptance. It is a step in
the test flow for every product manufactured. It doesn't matter if the
fab is captive or outside foundry.

When you, the end user, buy a semiconductor device, the first step in
the chain to bring you the magic is this "acceptance testing" of the
wafer. A test pattern of basic devices is evaluated. If the wafer is
deemed good, it goes to wafer test (terrible terminology here since that
sounds redundant) that actually checks the product dice. Again, the
acceptance testing only looks at the test pattern. But that is where the
devices are usually stressed since nobody will be buying the devices on
the test pattern. The idea behind this acceptance testing is to avoid
shipping a lot of bad wafers to the next step in the test flow. That is,
usually the acceptance testing is done at the fab. The wafers might not
even leave the fab if they really suck. Rather the fab notifies the next
person in the food chain that their wafer run bombed so they better
start another. Then parts go on hold and end users start to bitch.

Now back to the acceptance testing. Say you were buying a sports car.
Would you want the sports car you will be buying to be driven by some
maniac, beating the crap out of the engine and doing panic stops that
could warp a rotor. Or do you want to know that the factory occasionally
takes a vehicle and abuses it, but never sells the abused vehicles to
the public. Well it is similar for chips, though you never really know
the nitty gritty unless someone on the inside tells you. That is, the
semi may just stress the parts on the test pattern, or your actual part
may be stressed. I've seen it done both ways.

Once wafer tested, the good dice are mounted in the package. The
packaged part is tested. Often at high temperature and room temp, with a
QA sample at cold. Parts tested at temperature need a soak time, so you
usually do the room temperature test first, reject parts, then test the
rest at hot. A test flow could do 100% at cold, but that will cost you.
Cold testing is a pain. The parts handler jams due to ice or condensation.

So somewhere deep in the bowels of the company is the person that knows
the acceptance parameter for the reverse bias of your LED. And a
different person will have the history of that reverse bias test. There
are a lot of buzzwords, but probably "statistical process control" is
the most popular. Every test parameter from the testing the test pattern
is logged. The fab monitors all the test data to see if some parameter
is drifting. Maybe some machine is drifting and will be out of
calibration soon, etc.

This wafer acceptance is tricky business. Like I said, wafers that fail
may go into production if enough people sign off. If you scrap a lot,
people don't get parts. If you sign off on the failed parameters, the
parts may not be reliable. Some companies may go an extra step by
running a "factorial" during the initial wafer run. That is, they will
vary processing parameters in a carefully designed test matrix to
determine how sensitive a particular part is to a particular parameter.
Then if the a parameter is out of spec, you have actual test data to
show if it is significant or not.

 

[Bill Sloman]

Hi guys, I hope this is the last time for the following reversed
biased LED as Spad thread. (We've got to do a newsletter then manual,
so I need to at least wave my hands at the details.) I should als
apologize as this is mostly just my ‘thinking out loud’ to the SED.
So again here's the circuit.



+------+
| |
(+) |
Vbias - LED
(-) ^
| |
| +-----opa314-->out
| | buffer
GND 100k
|
GND

Vbias is ~24V (device dependent)

When light is shinned at the LED I see pulses.
the number of which changes linearly with light intensity.

There are two details for me to understand.
First I've been thinking about the data in terms of 'breakdown
channels' in the LED.

I assume they are independent, though I can imagine that some samples
might have overlapping channels.

As any one channel breaks down it starts to discharges the entire LED
capacitance. Also each channel has a different threshold voltage.
When the voltage across the LED falls below that threshold then the
breakdown stops.

Does this make sense geometrically? The depletion width is much less
than the square root of the area. (Is depletion width the right
term?)

The data for this model is manifold. First here's a 'scope
'histogram' of single photon events, 1 second persistence. ~5kHz count
rate.

http://bayimg.com/DamOLaAeG

with the trigger set down near ground.

I sent the same data into a comparator with adjustable reference
voltage and get a stair case type distribution of count rate vs
voltage.

(data posted on request)

If you trigger up high, then you just see one channel. The peak
height is approximately equal to the bias voltage minus some
'Vt' (threshold voltage). Here's a bunch of 'scope shots with
different bias voltages.

Vt =~23.1V

http://bayimg.com/EAmolAAeG

http://bayimg.com/eaMONAAeG

http://bayimg.com/eAmopaaeG

http://bayimg.com/FAMoAAaeG

I’m not sure how to explain why each channel has a different threshold
voltage.

The other thing I don’t understand is the turn on waveform. At low
bias voltage and for early times with higher bias voltage the turn on
looks linear with a slope that is related to the voltage peak... it
takes about 50 – 100ns to turn on. (See the data above.) Now what’s
weird is this turn on time seems to be independent of circuit
following the LED. It’s independent of the quenching resistor value
(100k ohm for the circuit shown) And also independent of the
capacitance to ground. The R and C loading of the LED has an effect
at later times and with higher bias voltages.

Here’s a screen shot where I added 12pF to ground in parallel with the
100k ohm resistor.

http://bayimg.com/JaMagaAeH

If I do the same with lower bias voltage then there is almost no
change in the waveform.

I was expecting a slower ramp. The opa134 opamp that is used as a
buffer has a input C of ~5pF.

Anyway thanks for reading and any thoughts are most welcome.

As I've posted here before, the one time I saw anybody run a LED reversed biased, the authors were trying to make a very narrow optical pulse at a well-defined instant to test a constant fraction discriminator.

http://ieeexplore.ieee.org/xpl/logi...re.ieee.org/xpls/abs_all.jsp?arnumber=4327450

Lo CC and Leskovar B IEEE Trans. Nucl. Sci. NS 93-105 (1974).