John Larkin said:
I was interested in discussing (this is a discussion group) what
future OSs might look like, and how multicore chips (which are
absolutely on the silicon peoples' roadmaps) would affect OS and
systems design.
Not many people seem to want to think about that.
I believe that this statement is not necessarily accurate. There are
many folks thinking quite a bit about how to leverage multiple
core processors. With a single socket Nahalem soon with 8 cores
(each with 2 threads), you're looking at 32-thread systems first
part of next year.
Linux, of course, has scaled well on systems containing up to 512
cores (and higher at SGI). Dynix/PTX scaled to 32 in the early
90's. Unisys had a 128 processor single system image in 1996
running a microkernel-based implementation of SVR4/ESMP.
AMD's Istanbul processor has 6 cores per socket today.
Much of what is done in the OS field is predicated on the
capabilities of the hardware being used. As X86-32 and X86-64
are by far the most prevalent architectures, that's where the
bulk of the attention is being paid.
SVM mode on AMD (and the VT-X mode on Intel) are quite exciting
for OS researchers as they provide the ability to really do a
"microkernel" operating environment; albeit it's now generally
refered to as a Hypervisor.
My strong belief is that you'll see in the near future every x86 system
from the desktop to the largest servers using a hypervisor as the
"security kernel" for the hardware, running COTS operating systems
such as Windows, Linux, OpenSolaris86 as guests. Even to the point where
invoking an application will automatically create and execute a new
instance of the operating system, just for that application.
The problems around leveraging the capabilities of high core counts
are currently in the application space, not the operating system
space, with the bulk of current applications being of the single
thread variety, although even legacy operating systems that don't
support multiple processing elements can still take advantage of
large core count systems by running multiple copies using a
hypervisor.
Meanwhile, you'll see the off-cpu I/O hardware becoming smarter
and (hopefully) requiring less from the operating system driver
(or even not requiring a driver at all). To a certain extent, EHCI,
UHCI and AHCI technologies are leading in this direction (at the
very least, a single driver can accomodate devices from multiple
suppliers, albeit still using a traditional memory-mapped I/O
mode).
I'd like to see a true off-load I/O processor such as many mainframes
used to have. Perhaps something based around SCSI Command Data Blocks
or the like (which have already been leveraged by USB, ATAPI et. al).
scott