Energy usage in electronics design languages

[Will]

Apologies for the question, but I am not an electronic engineer, so I
am not sure what to google for.

If I wanted to design a processor seperated into multiple parts so that
I could monitor each parts energy use in real-time, what would I design
it in? I am learning VHDL, so I can implement a non-energy optimising
version on an FPGA, but as far as I know I can't specify energy supply
in the normal language. Are there super sets of the language that do
what I want or would I need to use something else?


Will Pearson

 

[David Brown]

Apologies for the question, but I am not an electronic engineer, so I
am not sure what to google for.

If I wanted to design a processor seperated into multiple parts so that
I could monitor each parts energy use in real-time, what would I design
it in? I am learning VHDL, so I can implement a non-energy optimising
version on an FPGA, but as far as I know I can't specify energy supply
in the normal language. Are there super sets of the language that do
what I want or would I need to use something else?


Will Pearson

The power requirements for different parts of a processor will be
heavily dependant on the implementation - you are not going to be able
to build different parts on different FPGAs and find out anything
meaningful about the power requirements of a complete processor made
using standard processes.

Assuming you don't want to go to the expenses of serious full-scale
simulations, the easiest way to get at a vague idea would be to
implement the processor parts in an FPGA and use the design software's
power estimators to give you a guess - the Altera Quartus power
estimator is, I believe, the most accurate at a sane pricing level.

 

[Will]

The power requirements for different parts of a processor will be
heavily dependant on the implementation - you are not going to be able
to build different parts on different FPGAs and find out anything
meaningful about the power requirements of a complete processor made
using standard processes.

Assuming you don't want to go to the expenses of serious full-scale
simulations, the easiest way to get at a vague idea would be to
implement the processor parts in an FPGA and use the design software's
power estimators to give you a guess - the Altera Quartus power
estimator is, I believe, the most accurate at a sane pricing level.

Thanks for the answer. However I don't think I was very clear on my
initial question.

I am interested in optimising software, rather than hardware for energy
consumption in an online fashion (by a loose form of economic
evolution). A program is instantiated over many message passing
concurrent very small fine grained parallel processors with a tiny bit
of memory (a bit like smart memory).

This is getting a bit beside the point I want one program to be able to
read how much (software dependent) processing is being done by
processors in another area . So I was going to group processors in to
areas with a common power rail and monitor the energy usage of that
group and have that as an Input to the system, the more processing the
more energy usage. So I was wondering if there were EDL that allowed
this kind of design.

Thanks again for your help. I will want to make sure the processors
process efficiently as well as having efficient software on them.

Will Pearson

 

[Rich Grise]

This is getting a bit beside the point I want one program to be able to
read how much (software dependent) processing is being done by
processors in another area . So I was going to group processors in to
areas with a common power rail and monitor the energy usage of that
group and have that as an Input to the system, the more processing the
more energy usage. So I was wondering if there were EDL that allowed
this kind of design.

A profiler?

Good Luck!
Rich