On Mon, 15 Jun 2009 12:28:40 -0400, Phil Hobbs
Jim Thompson wrote:
On Mon, 15 Jun 2009 11:29:40 -0400, Phil Hobbs
[email protected] wrote:
On Jun 14, 7:32 pm, Phil Hobbs
[email protected] wrote:
On Jun 14, 6:51 am, Phil Hobbs
Ebrahim wrote:
Winfield Hill wrote:
Ahem. Well, in 32 posts, has anyone answered Ebrahim's
question? Which was, does a C-B junction make a good
low-leakage high-voltage diode, and my answer is yes.
Likely as low as 10pA, but I'd want to check specific parts.
It's the same question one asks before using a transistor at
extremely low collector currents. OK, not too many people
use BJT transistors at 10pA, for one thing they're very slow,
but it's surprising how well they work down in that territory.
Often when doing this trick, one wants very low capacitance,
and I've been disappointed with the high capacitance of the
usual candidates, e.g., 5pF. This is what steers people
back to the old PAD-1 beauties, spec'd at 0.5pF and 0.3pA
When one is in this pA territory, PCB leakage can be a big
problem, and teflon posts and in-air wiring are often used.
***Hello Winfield
:
Thank you very much for your technical and non-political answer.
So it makes sense to look for such a candidate among high frequency
transistors that should have low capacitance.
Thank you again.
Best wishes for you,
Ebrahim
The part of this that makes zero sense is the 100V part. Almost all op
amps, in fact AFAIK every single one ever sold, has PN junctions between
its inputs and its supply pins.(*) That's why the Absolute Maximum
Ratings section of datasheets specifies that you mustn't take their
inputs more than 0.3V outside the supplies.
Not everything on an IC maps well onto a schematic--e.g. schematics
don't show the parasitic SCR inherent in junction-isolated CMOS
processes. It's there, though, as you'll find if you try dumping 20 mA
into an input.
If you want the same sort of function provided by the input protection
diodes, without a big leakage problem, you can use something like this:
0 VDD
|
_
A
|
*---Ri------*--------Rf-----------*
| | |
GGG _ |
A |
| |
| |\ |
0-------------RRRRR---*---RRRRR---|+\ |
| \ |
| >---*-*---0
*---|- / |
| | / |
| |/ |
| |
*---Ri------*---Rf------*
|
GGG
(Noninverting shown because inverting is reasonably obvious, and
negative polarity left as an exercise for the reader.) You have to
scale the resistances to fit your problem. The idea is that the first
diode has nearly no voltage across it, and hence no leakage or
capacitive current. This isn't a complete solution, because it costs
you SNR eventually, but it's a lot better than nothing.
The diode needs almost no breakdown voltage at all--certainly not 100V..
Something like a BFT25 B-C junction (about 0.3 pF) will work great..
(WDNNS PAD-1!)
Cheers
Phil Hobbs
(*) Some chips, e.g. old CMOS->TTL converters use Zeners instead,
because their inputs are intended to be overdriven by volts. Also, some
rail-to-rail input op amps use charge pumps to allow them to run their
input stages on more than VDD-VSS.
--
Dr Philip C D Hobbs
Principal
ElectroOptical Innovations
55 Orchard Rd
Briarcliff Manor NY 10510
845-480-2058
hobbs at electrooptical dot nethttp://electrooptical.net
I'm not so sure about zener input protection. Generally when you need
to go above the rail, you just use a N mosfet with gate tied to source
and the drain going to the pad. You depend on the breakdown of the fet
to provide input protection. [If you are trying this in layout,
antenna rules may apply.]
Every time I investigated chip damage after ESD testing, it was always
due to over-voltage versus over current. I'm not a fan of high fields
(as found in reverse bias) in semiconductors. They seem to find the
weak spot in the junction and zap it. Forward biased junction might
have hot spots, i.e. current hogging, but in general they are pretty
rugged.
Transzorbs are pretty bulletproof--its job would be just to limit the
overvoltage across the series protection resistor long enough for the
polyfuse to switch. The resistor and the input diodes would protect the
input devices, at least if it were done right.
Cheers
Phil Hobbs
--
Dr Philip C D Hobbs
Principal
ElectroOptical Innovations
55 Orchard Rd
Briarcliff Manor NY 10510
845-480-2058
hobbs at electrooptical dot nethttp://electrooptical.net
I am referring to on-chip protection and failure analysis I've done.
I've used transorbs, but only on power rails. In any event, putting
zeners on chip isn't done to my knowledge, at least in MOS/BiCMOS.
See the slide "ground gate NMOS"
http://www.icims.csl.uiuc.edu/icap00/sjoshi_icap00.pdf
I'm sure it isn't done anymore, but check out the CD4049UB for an
example.
http://www.fairchildsemi.com/ds/CD/CD4049UBC.pdf, page 2.
Cheers
Phil Hobbs
Schematic "representations" on data sheets are often just that,
"representations". The "equivalent" IS done using a capacitively
coupled NMOS.
...Jim Thompson
I'm not surprised that it isn't a normal zener--but those parts don't
have normal protection diodes, which is where I was going with it. The
input of a CD4049 isn't the most robust thing in the universe, largely
because of having the weird protection network.
Cheers
Phil Hobbs
Most "modern" CMOS parts don't have classic diodes, particularly on
output pins.
...Jim Thompson
