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DaveC
Hello, just would like to check with you lot, what should be a simple logic
problem. Sorry if this is a little long I just trying to be sure I have got
this.
I'm trying to create a latched byte wide bi-directional port. I have two
MM74HC573's . I'll call them A and B. I have a 8 bit data bus broken by
these two chips. The outputs of A are connected to the inputs of B and
v.versa. I have two control lines Write (W) and Read (R).
Write is connected directly to A's Latch Enable, so when I do a write I set
W high and lower it when I'm done latching the bits and driving the line.
Read is connected to directly to B's LE and then to B's OE via a logic
inverter. Read is also connected directly to A's OE.... So when I need to
read the port I aet R high disabeling the output on A so I dont simply read
the last Write value and enable the normaly disabled B. When R is returned
low no latching will take place because OE is disabled via inverter and
Chip A will resume output state of the last latch write value.
Where is some of my wonderfull art.. I hope it shows what I was just
saying.
|-----------|
| |
| |
-------------| A |----------------
<< Data >>>> | D Q | >> data <<>>
---- |-----| |------| ------
| | | __| | |
W ---| |-----|LE OE|---- | |
| | |-----------| | | |
| | __________________| | |
| | | | |
| | | |-----------| | |
| | | | | | |
| | | | | | |
| ------| B |------/ |
| <<<< | D Q | << data |
----------| |----------|
| | __|
R ----------o--|LE OE|----
| |-----------| |
| |
|___[invert]_______|
This all seems fine to me, but I'm worried about propagation delays.
Inparticular when I Rise Read and A has data latched it seemed like short
somthing or get data from the A into B since Max output disable time is
23ns and LE is 15ns.
Hmm,
Thanks for your time.
DaveC
problem. Sorry if this is a little long I just trying to be sure I have got
this.
I'm trying to create a latched byte wide bi-directional port. I have two
MM74HC573's . I'll call them A and B. I have a 8 bit data bus broken by
these two chips. The outputs of A are connected to the inputs of B and
v.versa. I have two control lines Write (W) and Read (R).
Write is connected directly to A's Latch Enable, so when I do a write I set
W high and lower it when I'm done latching the bits and driving the line.
Read is connected to directly to B's LE and then to B's OE via a logic
inverter. Read is also connected directly to A's OE.... So when I need to
read the port I aet R high disabeling the output on A so I dont simply read
the last Write value and enable the normaly disabled B. When R is returned
low no latching will take place because OE is disabled via inverter and
Chip A will resume output state of the last latch write value.
Where is some of my wonderfull art.. I hope it shows what I was just
saying.
|-----------|
| |
| |
-------------| A |----------------
<< Data >>>> | D Q | >> data <<>>
---- |-----| |------| ------
| | | __| | |
W ---| |-----|LE OE|---- | |
| | |-----------| | | |
| | __________________| | |
| | | | |
| | | |-----------| | |
| | | | | | |
| | | | | | |
| ------| B |------/ |
| <<<< | D Q | << data |
----------| |----------|
| | __|
R ----------o--|LE OE|----
| |-----------| |
| |
|___[invert]_______|
This all seems fine to me, but I'm worried about propagation delays.
Inparticular when I Rise Read and A has data latched it seemed like short
somthing or get data from the A into B since Max output disable time is
23ns and LE is 15ns.
Hmm,
Thanks for your time.
DaveC