74HC573 Logic?

[DaveC]

Hello, just would like to check with you lot, what should be a simple logic
problem. Sorry if this is a little long I just trying to be sure I have got
this.

I'm trying to create a latched byte wide bi-directional port. I have two
MM74HC573's . I'll call them A and B. I have a 8 bit data bus broken by
these two chips. The outputs of A are connected to the inputs of B and
v.versa. I have two control lines Write (W) and Read (R).

Write is connected directly to A's Latch Enable, so when I do a write I set
W high and lower it when I'm done latching the bits and driving the line.

Read is connected to directly to B's LE and then to B's OE via a logic
inverter. Read is also connected directly to A's OE.... So when I need to
read the port I aet R high disabeling the output on A so I dont simply read
the last Write value and enable the normaly disabled B. When R is returned
low no latching will take place because OE is disabled via inverter and
Chip A will resume output state of the last latch write value.

Where is some of my wonderfull art.. I hope it shows what I was just
saying.

|-----------|
| |
| |
-------------| A |----------------
<< Data >>>> | D Q | >> data <<>>
---- |-----| |------| ------
| | | __| | |
W ---| |-----|LE OE|---- | |
| | |-----------| | | |
| | __________________| | |
| | | | |
| | | |-----------| | |
| | | | | | |
| | | | | | |
| ------| B |------/ |
| <<<< | D Q | << data |
----------| |----------|
| | __|
R ----------o--|LE OE|----
| |-----------| |
| |
|___[invert]_______|


This all seems fine to me, but I'm worried about propagation delays.
Inparticular when I Rise Read and A has data latched it seemed like short
somthing or get data from the A into B since Max output disable time is
23ns and LE is 15ns.

Hmm,
Thanks for your time.

DaveC

 

[Mario Trams]

Hi Dave,

DaveC wrote:

|-----------|
| |
| |
-------------| A |----------------
<< Data >>>> | D Q | >> data <<>>
---- |-----| |------| ------
| | | __| | |
W ---| |-----|LE OE|---- | |
| | |-----------| | | |
| | __________________| | |
| | | | |
| | | |-----------| | |
| | | | | | |
| | | | | | |
| ------| B |------/ |
| <<<< | D Q | << data |
----------| |----------|
| | __|
R ----------o--|LE OE|----
| |-----------| |
| |
|___[invert]_______|

D and Q at B are interchanged, right?

This all seems fine to me, but I'm worried about propagation delays.
Inparticular when I Rise Read and A has data latched it seemed like short
somthing or get data from the A into B since Max output disable time is
23ns and LE is 15ns.

Indeed, there might be some bus contention. But that can be
neglected very likely. When you rise Read, B might latch the
value driven by A for a moment. However, B is a latch and as long
as LE is 1, it will forward the input.
But the actual contention depends on what is attached to the busses.
In a (very) clean design - such as PCI - potential contentions
are avoided by introducing turn-around cycles where nobody is
driving the bus.

Anyways, I do not see the need for latches in your design.
Actually you make no use of them.
A simple 74xx245 transceiver would be sufficient, wouldn't it?
Or did I miss something?

Regards,
Mario

--
----------------------------------------------------------------------
Digital Force / Mario Trams [email protected]-chemnitz.de
[email protected]
Chemnitz University of Technology http://www.tu-chemnitz.de/~mtr
Dept. of Computer Science Tel.: (+49) 371 531 1660
Chair of Computer Architecture Fax.: (+49) 371 531 1818
----------------------------------------------------------------------

 

[DaveC]

Thanks Mario.

I'm putting together a port expander for PIC MCU's.. or just any MCU. So
the design bellow is is one half of a 16 bit data bus. I will also have a
16 bit address bus and 16 more control lines & Interupt support.

I need to latch the values only when I write info to the bus to interact
with ISA cards 512k sram, compact flash cards, you name it.

Thanks,
DaveC

Hi Dave,

DaveC wrote:

|-----------|
| |
| |
-------------| A |----------------
<< Data >>>> | D Q | >> data <<>>
---- |-----| |------| ------
| | | __| | |
W ---| |-----|LE OE|---- | |
| | |-----------| | | |
| | __________________| | |
| | | | |
| | | |-----------| | |
| | | | | | |
| | | | | | |
| ------| B |------/ |
| <<<< | D Q | << data |
----------| |----------|
| | __|
R ----------o--|LE OE|----
| |-----------| |
| |
|___[invert]_______|

D and Q at B are interchanged, right?

This all seems fine to me, but I'm worried about propagation delays.
Inparticular when I Rise Read and A has data latched it seemed like
short somthing or get data from the A into B since Max output disable
time is 23ns and LE is 15ns.

Indeed, there might be some bus contention. But that can be
neglected very likely. When you rise Read, B might latch the
value driven by A for a moment. However, B is a latch and as long
as LE is 1, it will forward the input.
But the actual contention depends on what is attached to the busses.
In a (very) clean design - such as PCI - potential contentions
are avoided by introducing turn-around cycles where nobody is
driving the bus.

Anyways, I do not see the need for latches in your design.
Actually you make no use of them.
A simple 74xx245 transceiver would be sufficient, wouldn't it?
Or did I miss something?

Regards,
Mario