which software can used to solve k-map?

[nick]

becase i have a 8 variables logic circuit ,i want to find a software to solve it
any kind of freeware can do that?
thanks!

 

[Paul Burke]

becase i have a 8 variables logic circuit ,i want to find a software to solve it
any kind of freeware can do that?

Lots, Lattice do one, Xilinx another, express the 8 inputs as logic
equations, run the HDL compiler, read the output. Or get OpalJr, or one
of half-a-dozen PLD compilers I've used, most of which are long forgotten.

But if it's a school exercise, use the freeware you already have- your
brain. An 8 input map is cumbersome, but not impossible, and you'll
soon realise why most people use HDLs these days.

Paul Burke

 

[Joel Kolstad]

But if it's a school exercise, use the freeware you already have- your
brain. An 8 input map is cumbersome, but not impossible, and you'll soon
realise why most people use HDLs these days.

I wasn't aware that Karnaugh maps could be (systematically) used for more
than 5 variables? Can they be? Back when I was in school we used the
'table method' (I've forgotten the real name) beyond 4.

And 4 is enough to convince people of the value of HDLs, I think!

 

[Jim Thompson]

I wasn't aware that Karnaugh maps could be (systematically) used for more
than 5 variables? Can they be? Back when I was in school we used the
'table method' (I've forgotten the real name) beyond 4.

And 4 is enough to convince people of the value of HDLs, I think!

Naaah! 8 is easy as long as you are neat with your partitioning. But
I'm going to have to learn some HDL of some flavor or another... a lot
of my recent CMOS analog chip designs require a lot of addressing,
sometimes 12-wide :-(

...Jim Thompson

 

[Active8]

Naaah! 8 is easy as long as you are neat with your partitioning. But
I'm going to have to learn some HDL of some flavor or another... a lot
of my recent CMOS analog chip designs require a lot of addressing,
sometimes 12-wide :-(

That's the road I statrted on and most of what I read indicated that
Verilog was the way to go - can't remember why - yet VHDL still
lives.

Would the group opine?

 

[Active8]

I wasn't aware that Karnaugh maps could be (systematically) used for more
than 5 variables? Can they be? Back when I was in school we used the
'table method' (I've forgotten the real name) beyond 4.

And 4 is enough to convince people of the value of HDLs, I think!

Yeah, and the K-map apps I've found are only free for lower numbers
of inputs, though some of them are pretty cool apps.

 

[Jim Thompson]

Yeah, and the K-map apps I've found are only free for lower numbers
of inputs, though some of them are pretty cool apps.

Karnaugh Map v4.4.5 (shareware), by Russell Sasamori, handles
5-inputs.

...Jim Thompson

 

[Terry Given]

becase i have a 8 variables logic circuit ,i want to find a software to solve it
any kind of freeware can do that?
thanks!

by the time you have found the s/w (if any), learned how to use it and
produced a result you could easily have solved the K-map by hand. Use a
pencil and a large sheet of paper. Stop trying to cheap on homework,
you'll never learn anything that way.

Cheers
Terry

 

[Joel Kolstad]

That's the road I statrted on and most of what I read indicated that
Verilog was the way to go - can't remember why - yet VHDL still
lives.

Would the group opine?

Hopefully not-too-inflammatory comparisons:

-- VHDL is somewhat more sophisticated in terms of what all the language
itself is capable of doing. But... much of that 'sophistication' is only
usable for testbenches as it isn't synthesizable.
-- VHDL is a VERY strongly typed language. (And unlike, say, C++, 'there's
no escape' via automatic conversion). This can be a major pain to people
who like loosely or untyped languages. Verilog is better in such cases.
-- VHDL is a lot more 'wordy.' If you like C, you'll like Verilog's syntax.
If you like Cobol, VHDL will be more to your liking.
-- If you learn one, you can pick up the other pretty quickly. (A book,
"HDL Chip Design" has a bunch of boilerplate design examples with VHDL and
Verilog side by side... nice.) My personal philosophy is to get the more
annoying one (VHDL) out of the way first, others might go for easier
(Verilog) first.
-- VHDL in the U.S. seems more popular on the east coast. Globally, VHDL
seems much more used in Europe than the US.

With both VHDL and Verilog, you're usually far more limited by your own
knowledge/cleverness and the limitations of the device you're targeting than
language.

---Joel Kolstad

 

[Ratch]

becase i have a 8 variables logic circuit ,i want to find a software to solve it
any kind of freeware can do that?
thanks!

I like to use Mahoney maps. Like Karaugh maps which are a specific
arrangement of a Venn diagram, a Mahoney map is just another arrangement.
The numbers within each block are the digital value of each term. Upper
case letters the variable and lower case letters are its inverse. I submit
a 4 and 5 variable map. There are two kinds. one has the order of ABCDE
and the other has the order EDCBA. Use the one that suits you. Make sure
you use a constant width font. Ratch

Following is a four term map:

ABCD
|-----b-----|-----B-----| |-----b-----|-----B-----|
|--d--|--D--|--D--|--d--| |--d--|--D--|--D--|--d--|
----*************************---*************************----
| | *0 *1 *5 *4 * | *0 *1 *5 *4 * | |
| c * * * * * c * * * * * c |
| | * * * * * | * * * * * | |
a --*************************---*************************-- a
| | *2 *3 *7 *6 * | *2 *3 *7 *6 * | |
| C * * * * * C * * * * * C |
| | * * * * * | * * * * * | |
----*************************---*************************----
| | *10 *11 *15 *14 * | *10 *11 *15 *14 * | |
| C * * * * * C * * * * * C |
| | * * * * * | * * * * * | |
A --*************************---*************************-- A
| | *8 *9 *13 *12 * | *8 *9 *13 *12 * | |
| c * * * * * c * * * * * c |
| | * * * * * | * * * * * | |
----*************************---*************************----
|--d--|--D--|--D--|--d--| |--d--|--D--|--D--|--d--|
|-----b-----|-----B-----| |-----b-----|-----B-----|
|--d--|--D--|--D--|--d--| |--d--|--D--|--D--|--d--|
----*************************---*************************----
| | *0 *1 *5 *4 * | *0 *1 *5 *4 * | |
| c * * * * * c * * * * * c |
| | * * * * * | * * * * * | |
a --*************************---*************************-- a
| | *2 *3 *7 *6 * | *2 *3 *7 *6 * | |
| C * * * * * C * * * * * C |
| | * * * * * | * * * * * | |
----*************************---*************************----
| | *10 *11 *15 *14 * | *10 *11 *15 *14 * | |
| C * * * * * C * * * * * C |
| | * * * * * | * * * * * | |
A --*************************---*************************-- A
| | *8 *9 *13 *12 * | *8 *9 *13 *12 * | |
| c * * * * * c * * * * * c |
| | * * * * * | * * * * * | |
----*************************---*************************----
|--d--|--D--|--D--|--d--| |--d--|--D--|--D--|--d--|
|-----b-----|-----B-----| |-----b-----|-----B-----|
|--d--|--D--|--D--|--d--| |--d--|--D--|--D--|--d--|
----*************************---*************************----
| | *0 *1 *5 *4 * | *0 *1 *5 *4 * | |
| c * * * * * c * * * * * c |
| | * * * * * | * * * * * | |
a --*************************---*************************-- a
| | *2 *3 *7 *6 * | *2 *3 *7 *6 * | |
| C * * * * * C * * * * * C |
| | * * * * * | * * * * * | |
----*************************---*************************----
| | *10 *11 *15 *14 * | *10 *11 *15 *14 * | |
| C * * * * * C * * * * * C |
| | * * * * * | * * * * * | |
A --*************************---*************************-- A
| | *8 *9 *13 *12 * | *8 *9 *13 *12 * | |
| c * * * * * c * * * * * c |
| | * * * * * | * * * * * | |
----*************************---*************************----
|--d--|--D--|--D--|--d--| |--d--|--D--|--D--|--d--|
|-----b-----|-----B-----| |-----b-----|-----B-----|

Following is a 4 term reverse map

DCBA
|-----c-----|-----C-----| |-----c-----|-----C-----|
|--a--|--A--|--A--|--a--| |--a--|--A--|--A--|--a--|
----*************************---*************************----
| | *0 *1 *5 *4 * | *0 *1 *5 *4 * | |
| b * * * * * b * * * * * b |
| | * * * * * | * * * * * | |
d --*************************---*************************-- d
| | *2 *3 *7 *6 * | *2 *3 *7 *6 * | |
| B * * * * * B * * * * * B |
| | * * * * * | * * * * * | |
----*************************---*************************----
| | *10 *11 *15 *14 * | *10 *11 *15 *14 * | |
| B * * * * * B * * * * * B |
| | * * * * * | * * * * * | |
D --*************************---*************************-- D
| | *8 *9 *13 *12 * | *8 *9 *13 *12 * | |
| b * * * * * b * * * * * b |
| | * * * * * | * * * * * | |
----*************************---*************************----
|--a--|--A--|--A--|--a--| |--a--|--A--|--A--|--a--|
|-----c-----|-----C-----| |-----c-----|-----C-----|
|--a--|--A--|--A--|--a--| |--a--|--A--|--A--|--a--|
----*************************---*************************----
| | *0 *1 *5 *4 * | *0 *1 *5 *4 * | |
| b * * * * * b * * * * * b |
| | * * * * * | * * * * * | |
d --*************************---*************************-- d
| | *2 *3 *7 *6 * | *2 *3 *7 *6 * | |
| B * * * * * B * * * * * B |
| | * * * * * | * * * * * | |
----*************************---*************************----
| | *10 *11 *15 *14 * | *10 *11 *15 *14 * | |
| B * * * * * B * * * * * B |
| | * * * * * | * * * * * | |
D --*************************---*************************-- D
| | *8 *9 *13 *12 * | *8 *9 *13 *12 * | |
| b * * * * * b * * * * * b |
| | * * * * * | * * * * * | |
----*************************---*************************----
|-----c-----|-----C-----| |-----c-----|-----C-----|
|--a--|--A--|--A--|--a--| |--a--|--A--|--A--|--a--|
----*************************---*************************----
| | *0 *1 *5 *4 * | *0 *1 *5 *4 * | |
| b * * * * * b * * * * * b |
| | * * * * * | * * * * * | |
d --*************************---*************************-- d
| | *2 *3 *7 *6 * | *2 *3 *7 *6 * | |
| B * * * * * B * * * * * B |
| | * * * * * | * * * * * | |
----*************************---*************************----
| | *10 *11 *15 *14 * | *10 *11 *15 *14 * | |
| B * * * * * B * * * * * B |
| | * * * * * | * * * * * | |
D --*************************---*************************-- D
| | *8 *9 *13 *12 * | *8 *9 *13 *12 * | |
| b * * * * * b * * * * * b |
| | * * * * * | * * * * * | |
----*************************---*************************----
|--a--|--A--|--A--|--a--| |--a--|--A--|--A--|--a--|
|-----c-----|-----C-----| |-----c-----|-----C-----|

Following is a 5 term map:

ABCDE
|---------------a---------------|---------------A---------------|
|-------c-------|-------C-------|-------C-------|-------c-------|
|---e---|---E---|---E---|---e---|---e---|---E---|---E---|---e---|
----*****************************************************************---
-
| | *0 *1 *5 *4 *20 *21 *17 *16 * |
|
| d * * * * * * * * * d
|
| | * * * * * * * * * |
|
b --*****************************************************************--
b
| | *2 *3 *7 *6 *22 *23 *19 *18 * |
|
| D * * * * * * * * * D
|
| | * * * * * * * * * |
|
----*****************************************************************---
-
| | *10 *11 *15 *14 *30 *31 *27 *26 * |
|
| D * * * * * * * * * D
|
| | * * * * * * * * * |
|
B --*****************************************************************--
B
| | *8 *9 *13 *12 *28 *29 *25 *24 * |
|
| d * * * * * * * * * d
|
| | * * * * * * * * * |
|
----*****************************************************************---
-
|---e---|---E---|---E---|---e---|---e---|---E---|---E---|---e---|
|-------c-------|-------C-------|-------C-------|-------c-------|
|---------------a---------------|---------------A---------------|
|-------c-------|-------C-------|-------C-------|-------c-------|
|---e---|---E---|---E---|---e---|---e---|---E---|---E---|---e---|
----*****************************************************************---
-
| | *0 *1 *5 *4 *20 *21 *17 *16 * |
|
| d * * * * * * * * * d
|
| | * * * * * * * * * |
|
b --*****************************************************************--
b
| | *2 *3 *7 *6 *22 *23 *19 *18 * |
|
| D * * * * * * * * * D
|
| | * * * * * * * * * |
|
----*****************************************************************---
-
| | *10 *11 *15 *14 *30 *31 *27 *26 * |
|
| D * * * * * * * * * D
|
| | * * * * * * * * * |
|
B --*****************************************************************--
B
| | *8 *9 *13 *12 *28 *29 *25 *24 * |
|
| d * * * * * * * * * d
|
| | * * * * * * * * * |
|
----*****************************************************************---
-
|---e---|---E---|---E---|---e---|---e---|---E---|---E---|---e---|
|-------c-------|-------C-------|-------C-------|-------c-------|
|---------------a---------------|---------------A---------------|

Following is a 5 term reverse map:

EDCBA
|---------------e---------------|---------------E---------------|
|-------c-------|-------C-------|-------C-------|-------c-------|
|---a---|---A---|---A---|---a---|---a---|---A---|---A---|---a---|
----*****************************************************************---
-
| | *0 *1 *5 *4 *20 *21 *17 *16 * |
|
| b * * * * * * * * * b
|
| | * * * * * * * * * |
|
d --*****************************************************************--
d
| | *2 *3 *7 *6 *22 *23 *19 *18 * |
|
| B * * * * * * * * * B
|
| | * * * * * * * * * |
|
----*****************************************************************---
-
| | *10 *11 *15 *14 *30 *31 *27 *26 * |
|
| B * * * * * * * * * B
|
| | * * * * * * * * * |
|
D --*****************************************************************--
D
| | *8 *9 *13 *12 *28 *29 *25 *24 * |
|
| b * * * * * * * * * b
|
| | * * * * * * * * * |
|
----*****************************************************************---
-
|---a---|---A---|---A---|---a---|---a---|---A---|---A---|---a---|
|-------c-------|-------C-------|-------C-------|-------c-------|
|---------------e---------------|---------------E---------------|
|-------c-------|-------C-------|-------C-------|-------c-------|
|---a---|---A---|---A---|---a---|---a---|---A---|---A---|---a---|
----*****************************************************************---
-
| | *0 *1 *5 *4 *20 *21 *17 *16 * |
|
| b * * * * * * * * * b
|
| | * * * * * * * * * |
|
d --*****************************************************************--
d
| | *2 *3 *7 *6 *22 *23 *19 *18 * |
|
| B * * * * * * * * * B
|
| | * * * * * * * * * |
|
----*****************************************************************---
-
| | *10 *11 *15 *14 *30 *31 *27 *26 * |
|
| B * * * * * * * * * B
|
| | * * * * * * * * * |
|
D --*****************************************************************--
D
| | *8 *9 *13 *12 *28 *29 *25 *24 * |
|
| b * * * * * * * * * b
|
| | * * * * * * * * * |
|
----*****************************************************************---
-
|---a---|---A---|---A---|---a---|---a---|---A---|---A---|---a---|
|-------c-------|-------C-------|-------C-------|-------c-------|
|---------------e---------------|---------------E---------------|

 

[Ken Smith]

I like to use Mahoney maps. Like Karaugh maps which are a specific
arrangement of a Venn diagram, a Mahoney map is just another arrangement.
The numbers within each block are the digital value of each term. Upper
case letters the variable and lower case letters are its inverse. I submit
a 4 and 5 variable map. There are two kinds. one has the order of ABCDE
and the other has the order EDCBA. Use the one that suits you. Make sure
you use a constant width font. Ratch

Following is a four term map:

ABCD
|-----b-----|-----B-----| |-----b-----|-----B-----|

Shouldn't this read b B B b?

 

[Ratch]

Shouldn't this read b B B b?

No, the map is correct. To prove it, simply read aBCD from the map.
It has a term value of 7. Ratch

 

[Mark Zenier]

becase i have a 8 variables logic circuit ,i want to find a software to solve it
any kind of freeware can do that?

Espresso, from the UC Berkely EE-CS department could do that. I found
it there about 7-8 years ago. Pretty strange data format (it was an
engine buried in some other design software for creating Programmable
Logic Array in digital ICs). It's the code used in some of the fancier
PALASM programs like ABLE and CUPL.

Mark Zenier [email protected] Washington State resident

 

[Michael]

Naaah! 8 is easy as long as you are neat with your partitioning. But
I'm going to have to learn some HDL of some flavor or another... a lot
of my recent CMOS analog chip designs require a lot of addressing,
sometimes 12-wide :-(

...Jim Thompson

I'm on your side of the fence, Jim.

I still have grid squares on overhead foils for up to 8x8 (I think),
printed with a laser printer. I used them for years to do all my
K-maps. Did do 8x8's ... several times. Write on the foils with grease
pencil; wipe 'em off when you're done.

 

[Paul Burke]

I wasn't aware that Karnaugh maps could be (systematically) used for more
than 5 variables? Can they be? Back when I was in school we used the
'table method' (I've forgotten the real name) beyond 4.

And 4 is enough to convince people of the value of HDLs, I think!

Use 'folding' rules. Draw the map so you can see the major transitions
easily (i.e. where the Gray code mirrors), then fold the map around
these lines - in your head of course. You can then group across the
layers according to the ususal rules, except instead of sqaures you get
cubes. As I said, cumbersome.

Paul Burke

 

[Tim Shoppa]

becase i have a 8 variables logic circuit ,i want to find a software to solve it
any kind of freeware can do that?
thanks!

Software? A 256-way lookup table.

Hardware? Not free, but a 256x1 PROM will do the job for just a dollar or two.
(Assuming you can find anyone still selling 256x1 bipolar PROM's, maybe use
a small part of a modern big EPROM).

If you have a bunch (meaning 40 or so) of TTL or CMOS multiplexers you
just build a 256:1 multiplexer.

With a very small amount of cleverness (and an inverter) a 128:1 multiplexer
can do the same job.

If this is homework, I suspect you're supposed to use your brain.

Tim.

 

[nick]

by the time you have found the s/w (if any), learned how to use it and
produced a result you could easily have solved the K-map by hand. Use a
pencil and a large sheet of paper. Stop trying to cheap on homework,
you'll never learn anything that way.

Cheers
Terry

8 variables are just inputs,my circuit has 8 inputs,and 9 outputs.Each
combination of input is match to exactly one combination of output,so
there are 8+9=17 variables, i think it is not a easy job if solve that
k-map by hand

 

[Jim Thompson]

8 variables are just inputs,my circuit has 8 inputs,and 9 outputs.Each
combination of input is match to exactly one combination of output,so
there are 8+9=17 variables, i think it is not a easy job if solve that
k-map by hand

That's a different kind of problem. Getting 8-inputs to _one_ of your
outputs is trivial, minimizing the whole structure is not.

...Jim Thompson

 

[Keith Williams]

Naaah! 8 is easy as long as you are neat with your partitioning. But
I'm going to have to learn some HDL of some flavor or another... a lot
of my recent CMOS analog chip designs require a lot of addressing,
sometimes 12-wide :-(

The subset of VHDL used in logic synthesis is pretty easy to learn.
The complete language is a bit harder. ;-)

 

[Keith Williams]

Hopefully not-too-inflammatory comparisons:

Nope, fairly well balanced.

-- VHDL is somewhat more sophisticated in terms of what all the language
itself is capable of doing. But... much of that 'sophistication' is only
usable for testbenches as it isn't synthesizable.

GENERATE is pretty powerful in synthesis. Does Verilog have an analog
to GENERATE?

-- VHDL is a VERY strongly typed language. (And unlike, say, C++, 'there's
no escape' via automatic conversion). This can be a major pain to people
who like loosely or untyped languages. Verilog is better in such cases.

Worse. ;-)

-- VHDL is a lot more 'wordy.' If you like C, you'll like Verilog's syntax.
If you like Cobol, VHDL will be more to your liking.

Actually PL/I is ADA in an EE wrapper. VHDL is very PL/I like. The
SELECT/WHEN construct is very PL/I like, strong types, etc. I don't see
it as being COBOL like at all. But you're right, Verilog looks a lot
like 'C'.

-- If you learn one, you can pick up the other pretty quickly. (A book,
"HDL Chip Design" has a bunch of boilerplate design examples with VHDL and
Verilog side by side... nice.) My personal philosophy is to get the more
annoying one (VHDL) out of the way first, others might go for easier
(Verilog) first.

I learned VHDL a few years back. It took a couple of weeks to pick up
enough to do synthesis. The hardest part for me (of the synthesizable
subset) was avoiding latches. Once I got my head around that I was off
and running. I've had no need for Verilog, so...

-- VHDL in the U.S. seems more popular on the east coast. Globally, VHDL
seems much more used in Europe than the US.

Yes, and VHDL is more common in FPGA development for some reason. I
originally picked up VHDL for an FPGA design (I had a choice). I chose
well, since I'm on the east coast (our processors are designed in VHDL
and moved over to that group).

With both VHDL and Verilog, you're usually far more limited by your own
knowledge/cleverness and the limitations of the device you're targeting than
language.

One would hope the language wouldn't get in the way of one's
cleverness. However, I believe VHDL is more powerful.