As I though we had agreed on earlier, what you posted is an IIR filter,
not an FIR filter. An FIR filter will have the form
out = sum-from-i=1toN( coefficient(i) * input(k+1-i) )
or in words, the current input times a coefficient plus the previous
input times another coefficient plus the next earlier input times yet
another coefficient... until you exhaust the set of coefficients.
Next input sample, you slide your set of saved input samples over by
one and do the same set of multiply-and-accumulates, which is how a DSP
can do the filter very efficiently. A typical DSP will fetch a new
coefficient and a new input from a circular buffer, multiply them
together, and add them into an accumulator, all in one instruction
cycle, and in many cases, the instruction can auto-repeat for N times
with practically no additional overhead.
But if the filter needs to have a lot of "memory" -- if its impulse
response takes a long time to die out -- then implemented as an FIR it
will take a long buffer, a lot of coefficients, and a relatively long
time to calculate unless you can do the multiplications and additions
all in parallel (such as digitally with an FPGA or in analog domain
with weighting resistors). And the IIR filter you have shown below has
a lot of "memory". If you hit it with an impulse, each of b0, b1 and
b2 becomes non-zero and will take a long time to die out. With no
further input, b0 will decay only 0.235 percent per sample. That means
it will take 295 sample periods for it to decay to half its original
value, and over a thousand sample periods to get down to 1/256th of the
amplitude of the input impulse. Depending on how accurately you wanted
to emulate the behaviour of that IIR filter, then, you'd probably need
a few hundred stages of sample delay, and a few hundred coefficients.
MAYBE you can do it in a much shorter FIR filter that will give you
acceptable performance, but it depends a lot on what's "acceptable."
Cheers,
Tom