VLSI question regarding parasitic-extracted layout

[Ant_Magma]

Hi, i'm not sure if this workgroups is suitable for VLSI questions but
since this is the closest i managed to found so i'm going to post it
here, hope you guys don't mind.

I'm working on a simple project of building a 6T SRAM cell. In the
question, the a section of the report requires "Simulation results of
the parasitic-extracted layout". Unfortunately, since my instructor is
not around for a few days i have no one to ask so i was hoping if
anyone here can explain to me what is it? And how do i obtain it?

I'm using the layout tool called MAGIC.

Thx guys....

 

[Jim Thompson]

Hi, i'm not sure if this workgroups is suitable for VLSI questions but
since this is the closest i managed to found so i'm going to post it
here, hope you guys don't mind.

I'm working on a simple project of building a 6T SRAM cell. In the
question, the a section of the report requires "Simulation results of
the parasitic-extracted layout". Unfortunately, since my instructor is
not around for a few days i have no one to ask so i was hoping if
anyone here can explain to me what is it? And how do i obtain it?

I'm using the layout tool called MAGIC.

Thx guys....

I don't know how to do it, but your layout tool can EXTRACT a netlist
from your layout that includes the parasitic capacitances (and
sometimes metalization resistances).

...Jim Thompson