Joel Kolstad said:
Thanks for all the help, Genome and Tim. I'll be gone this weekend but will
be able to get back to implementing this next week.
To answer your questions...
To reduce parts count, I'm using the ADC on-board the microcontroller and
using a 'digital' set point.
Sure... it's designed as a 25W supply with a 12V 'nominal' input voltage,
10V 'worst case' input (i.e., it's 25W with 0V input voltage, but 38W if
you really do have 12V around). The primary inductance is ~15.2uH, maximum
current is in the ballpark of 8-10A (depending on worst case/nominal case
input voltage). Output is then supposed to be 200V. The turns ratio of
~7.5:1 (sec
ri) gets me a maximum 'on' duty cycle of ~65%.
(After doing this design, I see why so many manufacturers are tempted to
rate their 12V input power supplies as having rated power output only down
to, say, 11.5V... pretty big drop there from 12V->10V!)
I understand & generally agree with the sentiment, but when you're building
a 'general purpose' power supply, how can you avoid some amount of
'approximation' (as opposed to rigorous analysis) when you can't reliably
predict exactly what the load (and hence the transfer function) is going to
be? Seems to me this is why PID is used so often -- it tends to behave
'reasonably' under most circumstance, even though I imagine you or other
posters could cite examples where, e.g., a power supply went unstable and
caught fire due to someone giving it a load the designers never anticipated.
Thanks, I'll study this on Tuesday!
---Joel
Hi Joel,
most smps error amplifiers are really PI controllers - opamp feedback
impedance Zf is usually a cap in parallel with RC. Some smps have a cap
across the upper resistor in the voltage divider - this adds derivative
action, giving a PID controller.
when designing an error amplifier, most people simply decide on the closed
loop bandwidth & phase+gain margins, then calculate the R's and C's
directly. They could, however, reformulate their equations in terms of Kp,
Ki (and Kd), solve for these controller gains, then calculate R's and C's
from the Kp, Ki expressions.
conversely IME, many control engineers (motor control in particular) dont
design anything, they just fiddle with Kp, Ki and Kd until the response
looks OK. Their PID controllers tend to have nice user interfaces, buttons,
LCDs etc, so changing gains is trivial and does not need soldering
irons.....but the better engineers design their controllers too (when the
plant is known).
thats interesting: WHEN THE PLANT IS KNOWN. The "plant" is the smps power
stage transfer function, which is known. the load is indeed unknown. IMO one
of the best books on control systems is "control of electric drives" W.
Leonhard, Springer-Verlag - its all real control loops, not mathematically
"nice" examples.
The advantages of PI(D) vs P control are all about steady-state and dynamic
behaviour. It is easy to show that a controller with proportional only
control has a finite, non-zero steady state error. This is because the
driving signal is just Kp*e where e is the error signal, Eref-Eactual. For
non-zero output, e must be non-zero, ie a steady state error must exist. As
Kp increases, this error gets smaller, but non-zero. Your error analysis of
Kp was great though - as Kp gets higher, the steady-state error decreases,
but the controller becomes more susceptible to noise. Not only that, but
enough Kp can make the system oscillate - in other words, over-correct one
way, then the other, and so on....the classic closed-loop oscillation.
you can improve the proportional controller by adding in feedforward -
calculate the steady-state duty cycle based in Vin, and add it to the output
of your P controller (actually this will improve all of your controllers).
A PI controller can be shown to have zero error in steady-state. If the
reference changes as a ramp (as opposed to the step it used to be) a PI
controller will follow the ramp with a steady-state error (control people
call this the static velocity error constant, Kve). PID controllers can
follow a ramp with zero error.
Likewise if the reference changes as a parabolic ramp (integral of ramp,
which is integral of step) a PID controller will follow it with a
steady-state error. higher-order controllers can of course follow this with
zero error.
In a smps, your reference doesnt change much, so PI control is usually
sufficient, and gives zero error in steady-state.
Because you have a sampled-data controller, the actual closed-loop bandwidth
you can obtain is quite a bit lower than your sample rate. A mate of mine
and I did an interesting experiment a few years ago. Using a frequency
response analyser, we measured the response of an RC filter (1k, 1uF,
Tau=1ms, Fo=159.15Hz), a 1st-order IIR filter Fs=4kHz using backward
difference transform, and the same filter using a bilinear transform, with
and without frequency warping.
The resultant plots are very interesting - I will put it on s.e.d. The
bilinear-transform IIR filter didnt change when frequency warping was added,
as expected given Fs=4kHz, Fo=159Hz. The BLT IIR and RC gains were identical
up to 500Hz, within 2dB at 1kHz, with BLT droppping to 18dB below RC at
2kHz, as expected (Nyquist frequency).
The BD IIR gain was off by about 1dB at 159Hz (measured Fo=184.3Hz), 2dB
above RC at 500Hz, 3dB above RC at 1kHz and 5dB above RC at 2kHz.
Phase, however, is where it got real interesting - BLT IIR was 1 degree more
than RC at 500Hz, 2 degrees at 1kHz, and about 5 degrees at 1900Hz - it shot
to hell at 2kHz. Clearly a BLT IIR filter adds bugger all phase shift right
up to nyquist, at which point it turns to crap.
The BD IIR filter was another story entirely! about 10 degrees LESS phase
shift than RC at 159Hz, 20 degrees less at 400Hz, and it then started going
the wrong way - 44 degrees less phase shift at 1kHz, about 80 degrees at
near 2kHz. This backward-difference transformed filter is absolute rubbish
above about Fs/10, and even then gets phase wrong by 20 degrees or so.
the difference between a BD IIR and a BLT IIR is a single addition. no
prizes for guessing which approach we used.
Also, dont forget to put an antialiasing filter in your ADC signal path.
Make sure "nothing" comes in above Fs/2, like say switching noise. Also, if
you can, synchronise your ADC sampling with the centre of your pwm output
(easy to do with count-up-count-down ie symmetric PWM), as that will be as
far away as possible from the switching edges, which are what generates all
the noise.
No reason why your smps closed-loop bandwidth has to be very good - I worked
with a design once that had a 1Hz bandwidth - a moving-coil meter would show
the transient response! As long as it does your job.....
BTW, go look at what happens to your flyback converter when your first turn
it ON. switch turns on at max. D, charging L up to Ipk (or thereabouts),
dIprim/dt = Vprim/Lprim. During flyback, energy dumps into UNCHARGED output
capacitor Cout through diode D. dIsec/dt = Vsec/Lsec = (Vout+Vd)/Lsec BUT
Vout = 0 so dI/dt is MUCH less than you expected. Therefore only a small
amount of energy gets dumped in Cout, the rest stays in Lsec (low dIsec/dt
means it doesnt discharge very rapidly). When your switch NEXT turns on, Ip
starts off at close to Ipeak, NOT zero. Eventually Cout charges to Vout, and
dIp/dt = dIs/dt (or thereabouts)
If you do not have a dedicated peak current trip, and instead have a fixed
duty cycle, you WILL blow up your smps - Iprim just keeps ramping up and up.
Sure, each time Vout rises a bit more so dIsec/dt gets a bit bigger, but it
often takes 10-15ms for a flyback to start up properly, ie a few thousand
cycles. Lprim will saturate WAY before then, probably about the 2nd pulse.
This is one of the reasons soft-start circuits are used. In your micro,
slowly ramp D up at turn-on. It would also be a good idea to incorporate a
peak primary current limit - say a flip-flop + comparator, or maybe your
micro can do that itself somehow.
cheers
Terry
