Serial communication problem.

[HellasTechn]

I have tested the max3232 that i have on breadboard with 0.4uf caps and different test with 1uf caps (could not get 0.1 electrolytic) and i got the same 5V cd on the input of the rs232 but 0 volt on the output of ttl.

 

[Harald Kapp]

Because BE junction is reverse biased.

Reverse biasing means an inverse voltage. With an open input there is no inverse voltage.Dorke is heading for a different explanation.

the rs232 signal is >-3V (idle state)

No, it is idle <-3 V.
I'm sure we mean the same, just being picky a bit

Is it not oposite than what we need for TTL ?

You're mixing things a bit.
By TTL you mean the definition of "allowed" logic levels.
Even when this has been calrified, there is still the matter of positive and negative logic or active high and active low states.

A typical UART interface uses active high signals (positive logic), eaning a logic '1' is represented by a voltage >= 2 V on an input and a logic '0'is represented by a voltage <= 0.8 V on an input.
RS232 uses completely different voltages to represent logic levels: A logic '1' is represented by a voltage <= -3 V, a logic '0' is represented by a voltage >= +3 V.
The level translator in the circuit abve does exactly this transformation from RS232 to TTL. This page explains it well with an intuitive diagram.

 

[HellasTechn]

Reverse biasing means an inverse voltage. With an open input there is no inverse voltage.Dorke is heading for a different explanation.

Correct. with open base there is no bias at all. Still the same outcome though.

By TTL you mean the definition of "allowed" logic levels.

Yes. 5V logic 1 and 0V logic 0.

You're mixing things a bit.

I think i got it now. The circuit actually works as i thought but it's just that TTL signals are "active low" (logic 1=0V and logic 0=5V) so it's only natural that while VBE is >-3 volts the transistor will be open and TTL output will be equal to VCC = 5V and vice versa.

Then again why the output of the max3232 is idling at 0V ?

 

[Harald Kapp]

with open base there is no bias at all.

The base is not open. Look at the resistors connected to the base...

but it's just that TTL signals are "active low"

Actually the TTL side of a UART uses positive logic. Logic '1' = 5 V, logic '0' = 0V (ideally).
The idle state of a UART signal is logic high which is equivalent to < -3 V (not > - 3 V as you write) on the RS232 line.

Then again why the output of the max3232 is idling at 0V ?

Which output? TTL side or RS232 side?
For which input signal?
Figure 7 of the datasheet shows the signal waveforms to be expected.

 

[dorke]

Because BE junction is reverse biased.
What i dont get now is this : ttl signal is idle 0V and high 5V
the rs232 signal is >-3V (idle state), with the ec open the output will read 5volts and when rs323 pulses high >+3V then ec is closed affectively grounding vcc through the resistor so the output reads 0V.
Is it not oposite than what we need for TTL ?
Thank you, i will read them.

Another practice question for you:
Looking at #34 circuit,
Can you "estimate" at what rs232 input voltage will the output be 0-volts?

"ttl signal is idle 0V and high 5V".
Well not quite,there is no "idle" definition for TTL.
It has 2 logic levels "0" and "1",their interpretation could be anything you like.
So the states of the input-output are not "opposed" to TTL.
Like I said in #38:
"The functionality is of a logic inverter.
Unlike a "pure logic device" ,it has different input and output voltage levels i.e it performs voltage shifting/translation."

The way to interpret this is :
Output at 0 volts means the RS232 input is at Space state.
Output at vcc volts means the RS232 input is at Mark state.

 

[hevans1944]

What i dont get now is this : ttl signal is idle 0V and high 5V
the rs232 signal is >-3V (idle state), with the ec open the output will read 5volts and when rs323 pulses high >+3V then ec is closed affectively grounding vcc through the resistor so the output reads 0V.
Is it not oposite than what we need for TTL ?

The relationship between TTL voltage levels for logic levels of "zero" and "one" and RS232 voltage levels for idle (mark) <-3 V and high (space) >+3 V is what it is. So, yes, disregarding the magnitude of the TTL versus RS-232 signals, the polarity is inverted. So what? You process the TTL signals as you wish, usually with a Universal Asynchronous Receiver/Transmitter (UART) integrated circuit, so if a logic inverter stage is required, so be it.

The terms "mark" and "space" are leftovers from hard-wired telegraph keying, where normally a telegraph circuit remained closed on both ends, thus allowing a solenoid to be actuated to make a mark from an ink pen on a moving strip of paper. This practice continued when electro-mechanical teletype machines replaced paper tape for hard-copy text results. The normal condition (no data being transmitted) was a closed circuit, usually a 20 mA constant-current circuit. Opening this circuit caused the teletype to "chatter" because no code characters were being received.

For land-line telegraphy, the telegraph key was equipped with a means to "short" the key contacts when the key was in the up or de-actuated position. To send a message, the circuit was opened on the transmitter end by removing the short" across the key contacts, thereby creating a space on the paper tape. Tapping the key periodically closed the circuit, thus creating a mark on the paper tape each time the telegraph key was depressed.

The RS-232 standard evolved separately from wired telegraphy, but the terms "mark" and "space" were retained. That a "mark" is represented by a negative voltage, with respect to ground, and a "space" is represented by a positive voltage, with respect to ground, has nothing to do with transistor-transistor-logic (TTL) and was, IMO, a totally arbitrary decision.

 

[dorke]

Hop,

A few notes:

1. The 20mA current, was and still is called "Current Loop".

2. Here is an article on the History of Mark and Space.

3. Here is ITU-T V.1 ,a standard which explains why and how were the voltage levels and logic levels of Mark and Space chosen.
Surprise... not arbitrarily, and goes back to 1960!

 

[HellasTechn]

The RS-232 standard evolved separately from wired telegraphy, but the terms "mark" and "space" were retained. That a "mark" is represented by a negative voltage, with respect to ground, and a "space" is represented by a positive voltage, with respect to ground, has nothing to do with transistor-transistor-logic (TTL) and was, IMO, a totally arbitrary decision.

It's clear to me that TTL has purely to do with voltage levels. The way a system preceives theese voltages is a different story.

I will get back with a new diagram so you can all advice me further ! Its just that i am short on time theese days thats why its taking me long to write back.

Thank you ALL !

 

[HellasTechn]

So what? You process the TTL signals as you wish

True, only in my case the TTL board use active high signals (logic 1 = +5V).

What if i use a PNP transistor to make an rs232 to ttl converter that will not invert the signal ?

something like the diagram pictured below.

My thinking is that when the rs232 signal will be positive it will be grounded through D and R1 and the BE junction will be reverse biased, keeping EC open.

When rs232 signal will be negative, D will be reverse biased and BE junction will be forward biased, closing EC.

Am i thinking correctly ?

 

[Harald Kapp]

Am i thinking correctly ?

Correct in terms of the descriptin of the circuit. Incorrect in terms of the conversion from RS232 to TTL.

A voltage level of less than -3 V on the RS232 translates to a voltage level > 2.4 V on the TTL side.
A voltage level > +3 V on the RS232 side translates to a voltage level < 0.4 V on the TTL side.
This is what the circuit as suggested does.
Your circuit translates RS232 > +3 V to TTL > 2.4 V and RS232 < -3V to TTL < 0.8 V. This is not conform with the standard.

Imagine the other side, the sender: A TTL logic high will be sent as a voltage < -3 V on the RS232 line. You want this to be converted back to TTL logic high on the receiving end. not to TTL logic low, don't you?

 

[dorke]

Well,
Again not quite correct.
The "reference voltage" for the RS-232 input to compere with should be zero volts.
It is not the case in your circuit,Vbe is not "referenced" to ground but rather to "VCC".
Look at the correct diagram below.
The B-E junction is the one to be protected,look a the direction of the diode.

Note:
If you connect directly to a UART on your TTL board, it is usually active low,not active high !

 

[HellasTechn]

Your circuit translates RS232 > +3 V to TTL > 2.4 V and RS232 < -3V to TTL < 0.8 V. This is not conform with the standard.

Why would that happen ? because of the transistor properties ? is it not driven directly to saturation and cutoff areas ? The way i see it in post #24 picture 1 the voltage range is from -9V to +9V RMS so i dont think i will have such problem.

The B-E junction is the one to be protected,look a the direction of the diode.

Why do i have to connect emitter to "gnd" and collector to vcc ?

 

[dorke]

"Why do i have to connect emitter to "gnd" and collector to vcc ? "


I'm re-posting from #45:
"Another practice question for you:
Looking at #34 circuit,
Can you "estimate" at what rs232 input voltage will the output be 0-volts?"

Add the same question for the output at "Vcc".

Try to answer that question for the inverting circuit.
and than for the non-inverting one for the PNP connected in the 2 ways above.

What is the "0 volts" output you are getting?
Surprised ?

If you answer the questions ,
it will enlarge your understanding of BJT's and answer your question...

 

[Harald Kapp]

Why would that happen ?

To keep in line with dorke's approach:
Consider the case of a negative voltage on the base (e.g. -3 V from teh RS232, fivided by R1/R2). Will ethe transistor be on of off? What will be the output voltage?
Consider the case of a positive voltage on the base. Will ethe transistor be on of off? What will be the output voltage?

 

[HellasTechn]

Consider the case of a negative voltage on the base (e.g. -3 V from teh RS232, fivided by R1/R2). Will ethe transistor be on of off? What will be the output voltage?

I am not sure...

Consider the case of a positive voltage on the base. Will ethe transistor be on of off? What will be the output voltage?

if its large enough it should be off because BE will be reverse biased and output should be Vcc

 

[HellasTechn]

Funny this topic started as communication problem and is ending as transistor tutorial. Maybe we should move theese posts to an other topic probably called Transistor lessons ?

This is really very interesting and i thank you all for helping me out this way !

 

[HellasTechn]

"Why do i have to connect emitter to "gnd" and collector to vcc ? "


I'm re-posting from #45:
"Another practice question for you:
Looking at #34 circuit,
Can you "estimate" at what rs232 input voltage will the output be 0-volts?"

Add the same question for the output at "Vcc".

Try to answer that question for the inverting circuit.
and than for the non-inverting one for the PNP connected in the 2 ways above.

What is the "0 volts" output you are getting?
Surprised ?

If you answer the questions ,
it will enlarge your understanding of BJT's and answer your question...

I will work on it... I am going to breadboard the circuit with a 2n2222 that i have. For Vcc i will use a 9V battery and an 7805Vreg. For input signal i am going to use my bench psu so Vbe will be a dc voltage from my psu. forward bias would be negative of psu to emitter and positive to base and vice versa to simulate negative voltages.
I will then scope the output and write back what i observe

 

[dorke]

Funny this topic started as communication problem and is ending as transistor tutorial. Maybe we should move theese posts to an other topic probably called Transistor lessons ?

This is really very interesting and i thank you all for helping me out this way !

I think we are actually dealing with the same topic,"A design of an RS232 receiver".
This is done from several angles, so could stay as is .

Let's take a step by step examination:

look at your circuit with input voltage at "Space" (>+3V).

What is the output voltage Ve(Emitter to GND)?
Ve=Vd+Vbe=0.7+0.7=1.4Volts.
Is the Tr. saturated here?

Is this voltage a legal TTL "0" level?
NO,it is not!!!
Actually this is the worst case for TTL level possible, about mid point between "0" and "1",
A TTL input may interpret it as either 0 or 1.

Can you do the same for the case of the input voltage at "Mark" (<-3V).

 

[dorke]

I will work on it... I am going to breadboard the circuit with a 2n2222 that i have. For Vcc i will use a 9V battery and an 7805Vreg. For input signal i am going to use my bench psu so Vbe will be a dc voltage from my psu. forward bias would be negative of psu to emitter and positive to base and vice versa to simulate negative voltages.
I will then scope the output and write back what i observe

No ! you shouldn't connect a PSU directly to the Tr. like you discribe, it may destroy it!
Use it with the biasing resistors as shown in the circuits.

There is no need to test the circuits "under voltage",
They should be analyzed "on paper" first, it is not complicated,and we can help you with that.

 

[HellasTechn]

No ! you shouldn't connect a PSU directly to the Tr. like you discribe, it may destroy it!
Use it with the biasing resistors as shown in the circuits.

That's what i was planning to do anyway.

There is no need to test the circuits "under voltage",
They should be analyzed "on paper" first, it is not complicated,and we can help you with that.

Yes, your help is highly appreciated! I unfortunately i have difficulties understanding the math.
Ho well, i am pretty sure i need to read the PDF files on post #39 throughly before we can continue this tutorial.

P.S.
Shouldn't we move it to a different thread?