Selecting Mosfets for Lowest Power Dissipation

[[email protected]]

I'm currently trying to find an effective way to select a mosfet with
the lowest power dissipation for the following circuit values:
Id=2A
Vd=270V
f=100khz
D=40%

Mosfet Driver Specs
Claims up to 2A peak gate drive
Tf = Tf = 14nS with 1nF load

Rdson is just a conduction loss.
Gate capacitance is the main cause of switching loss due to slowing
down driver rates. <<Not sure about that..

Rdson and gate capacitance are inversely proportional for mosfets?
<<Not sure about that too..
If so...
By finding the balance between Rdson and gate capacitance, I could get
less total power dissipation.

In that case...
Is there a figure of merit...Maybe like Ciss/Rdson? I just go for the
smallest number?

I've been looking at the SPP21N50
Rds(on) 0.19 ohms
Ciss = 2400pF
This mosfet has a great Rdson but I wonder if I could get less
dissipation with more Rdson and less Ciss?

What's a good selection procedure?

I''m hoping for some hints while I google for answers.
D from BC

After reading the book "Switching Power Supplies A to Z" by Sanjaya
Maniktala, I derived the following expression for the switching loss
(Pm) in the Miller region. All the parameters can be found on a
typical mosfet data sheet.

//Back-of-envelope calculation of Miller-plateau crossover loss.
//The Miller loss omits the loss as the drain current swings at
VDS=Vin constant.
//The Miller loss is the largest switching loss which occurs as VDS
swings at IL constant
theta=Qgs/(Qg-Qgd);//Ubiquitous gate-charge factor appearing in Miller
loss formula
Pm=(IL*Vin*Qgd*Rdrive*f/(2*Vdrive))*(1/(1-theta)+1/(theta-Vsat/
Vdrive));
where,
//Parameters (SI units)
f=500.0e3;//Switching frequency
Vdrive=4.5;//Gate driver voltage high voltage
Vsat=0.0;//Gate driver logic low voltage
Rdrive=2.0;//Lumped drive impedance plus mosfet gate resistance Rg
Vin=15.0;//Input voltage for the buck VDS(t=0) for all topologies
IL=22.0;//Free-wheeling diode current
//Mosfet parameters at a typical VDS
Qg=36.0e-9;//Gate charge factor Si4442DY, VDS=15V, VGS=4.5V, ID=22A
Qgs=8.0e-9;//Gate charge factor Si4442DY, VDS=15V, VGS=4.5V, ID=22A
Qgd=10.5e-9;//Gate charge factor Si4442DY, VDS=15V, VGS=4.5V, ID=22A

Stephen
http://www.stebla.pwp.blueyonder.co.uk

 

[D from BC]

After reading the book "Switching Power Supplies A to Z" by Sanjaya
Maniktala, I derived the following expression for the switching loss
(Pm) in the Miller region. All the parameters can be found on a
typical mosfet data sheet.

//Back-of-envelope calculation of Miller-plateau crossover loss.
//The Miller loss omits the loss as the drain current swings at
VDS=Vin constant.
//The Miller loss is the largest switching loss which occurs as VDS
swings at IL constant
theta=Qgs/(Qg-Qgd);//Ubiquitous gate-charge factor appearing in Miller
loss formula
Pm=(IL*Vin*Qgd*Rdrive*f/(2*Vdrive))*(1/(1-theta)+1/(theta-Vsat/
Vdrive));
where,
//Parameters (SI units)
f=500.0e3;//Switching frequency
Vdrive=4.5;//Gate driver voltage high voltage
Vsat=0.0;//Gate driver logic low voltage
Rdrive=2.0;//Lumped drive impedance plus mosfet gate resistance Rg
Vin=15.0;//Input voltage for the buck VDS(t=0) for all topologies
IL=22.0;//Free-wheeling diode current
//Mosfet parameters at a typical VDS
Qg=36.0e-9;//Gate charge factor Si4442DY, VDS=15V, VGS=4.5V, ID=22A
Qgs=8.0e-9;//Gate charge factor Si4442DY, VDS=15V, VGS=4.5V, ID=22A
Qgd=10.5e-9;//Gate charge factor Si4442DY, VDS=15V, VGS=4.5V, ID=22A

Stephen
http://www.stebla.pwp.blueyonder.co.uk

So...the switching loss calculation includes Qgd, Qgs and Qg...or in
other words, every pin to pin capacitance.

Like someone posted...
I'm probably going to select a bunch of mosfets with the right Vds and
Id ratings. ( Price will be a factor at some point.)
Then try'm all in LTSPICE.
(.step mosfetlibrary 1 100 1???) <<Fictional directive but purpose
should be understood... I might make this a new post topic since I'm
new to LTspice.
I estimate about 100 modern mosfets total from multiple sources.
(Vdsmin=300, Idmin=2A)
Say 1min/sim.
So.. I should get my results in about 2 hours..
I'll get the winning mosfet as it applies in my app...
But the set up is a PITA and I'm guessing it'll take all day to
collect models and figure how to configure ltspice.
D from BC

 

[john jardine]

John I'm still trying to work out how to contact you by email. Have you
done a seacrh on jjdesigns? Quite amusing really.

I'll try again. (3rd attempt)
Don't know what the f**** happening to the stuff I send but about 6 posts
have gone AWOL over the past week including a hand crafted long nasty rant
about FPGAs.
Never mind. It's ...

john.jardine (the "at" symbol) idnet.co.uk

As an internet device, the "jjdesigns" was bought up in the early days by a
landscaper and dress maker. Watching how this week's been turning out, I'd
probably been better off also following some nice, uncomplicated, detail
free, stress free, son-of-the-soil type activity

 

[legg]

I found this:
Taken from
http://www.maxim-ic.com/appnotes.cfm/appnote_number/1832
"Once you have narrowed the choice to a specific generation of MOSFET
based on cost (the cost of a MOSFET is very much a function of the
specific generation to which it belongs), select the device within the
generation that will minimize power dissipation. This is the device
with equal resistive and switching losses. Using a smaller (faster)
MOSFET increases resistive losses more than it decreases switching
losses; a larger (low RDS(ON)) device increases switching losses more
than it decreases resistive losses."

Neat.....50 50 on the losses...

Rough formula for switching loss:.
Pdswitching = (Crss x Vin^2 x fsw x Iload) / Igate
(Igate is the MOSFET gate-driver's sink/source current at the MOSFET's
turn-on threshold (the Vgs of the gate-charge curve's flat portion).)

How much does Crss vary among mosfets?
What a PITA...I also have to estimate Igate..
Once I solve for Pd then I can calculate the corresponding Rdson..
Then I have 2 specs to pick a mosfet out of a table of mosfets.

The 'total gate charge' spec includes Crss effects on the duration of
the gate voltage plateau during switching. Unfortunately this is
usually a 'typical' value, at a nominal drain starting voltage.

Keep in mind that you may not be permitted to witch things as fast as
you might want, simply due to the excess noise it may generate in
dependant rectifiers - decoupling these effects with series limiting
elements (beads and such) may be a worthwhile study in a functional
breadboard.

Depending on the budget, methods of assisted switching or zero-voltage
topologies could prove effective at battling noise or temperature
rise.

RL

 

[D from BC]

After someone posted a formula I found:
http://www.fairchildsemi.com/an/AN/AN-6005.pdf

So I did some estimates instead of a bunch of spice simulations...

Input data:
Vd= 270V
Id= 2.4A
Idriver=2A
f=100khz
D= 40%

All these Digikey stock parts have about the same total power loss..
FCP20N60
FDH44N50
FQP9N50
FCB11N60
FCB20N60
FCP7N60
SPA08N50C3
SPA12N50C3
SPP16N50C3X

From the above:
Qg(total) ranged from 18nC to 90nC and Rdson ranged from 0.11 to 0.73
ohms..
The winner at an estimated 2.4Watts is Fairchild's Superfet at
Qg(total) = 40nC and Rds(on) =0.32ohms..

So...I could run the math again with a more powerful mos driver...
(Micrel was mentioned with 6A peak drive current.)

Or....
I'm wondering about paralleling mosfets.....
Maybe I could parallel a bunch of speedy low charge mosfets until the
conduction losses are minimal.
Is this practiced in smps design?
Does this explain those seemingly useless high Rds(on) mosfets?
D from BC