Project design help (gates, d-latch questions)

[Macboost]

Hi all!

Currently working my way through a project assigned for class, heres the basics:
1) when switches 1,2,3,4 are thrown in that order, you can throw switch 5 to light the diode.
OR
2) when switches 1,2,3,4,6,7,8 are thrown (in that order), you can then throw switch 5 to light the diode.
OR
3)when switches are thrown in this order 1,6,2,7,3,8,4 then 5, the diode should light.

Any incorrect order of switches and the diode should not light.
-can use any logic gates, inverters and clocked d or j/k flip flops

Basically, its a three step process.
-Design ckt to light when 12345 are thrown
-design ckt to take 1,2,3,4 switches inputted into a ckt that contains logic for switches 6,7,8,
-merge the two ckts together so that when either 1,2,3,4,5 are thrown or 1,2,3,4,6,7,8,5 are thrown, diode lights.

The problem I'm having is taking the 6,7,8 output and combining it with the 1,2,3,4 ckt so that they work together correctly. I guess I just cant figure out which combo of gates to use. Obviously, it cant just be a simple OR gate, because the ckt should not light when switches 6,7,8 are thrown without previously having thrown switches 1,2,3,4. Switch 5 is the "ignition" switch. I have attached my design so far. Any thoughts?
So basically,
1+2+3+4+5=diode on
OR
1+2+3+4+6+7+8+5 = diode on
Any of those out of order or not flipped should and the diode should stay off.

If you could, please take a look at my design and feel free to ask any questions or make suggestions.

 

[Macboost]

Higher resolution schematic attached. Made what I thought was some progress, but it is still flawed because while switch sequence 12345 works and sequence 12346785 works, it also still starts with 1234675 or even 123465. Gates, gates, gates...

 

[(*steve*)]

Here's a hint.

The 1-2-3-4-5 circuit should give a false output if any switches are pressed after 1-2-3-4-5. If this is true for both circuits (the other one will produce a fail if anything happens after 1-2-3-4-5-6-7-8) then what is the simple way to combine them?

 

[Macboost]

I'm thinking along these lines:

 

[Laplace]

Maybe there is a different way to look at this problem. We have the occurrence of a sequence of logic signals and need to reach the end of the sequence without an error condition. I would propose a functional device, call it an Error Sequence Block, that can be wired in sequence to search for any error condition that will inhibit the final start signal. Each ESB will have a condition input 'C' and a pre-condition input 'P'; an error state will be detected if the condition occurs without the pre-condition being true (ERROR = C AND NOT P). Each ESB will also have an Error Carry Input 'Eci' and an Error Carry Output 'Eco' (Eco = Eci OR ERROR).

So for sequences 12345 or 12346785, START = (Q5 AND NOT Eco) AND (Q8 OR (Q4 AND NOT Q6)). For the sequence 16273845 there would need to be another string of ESBs with (Eco1 AND Eco2) inhibiting Q5 since following one sequence will guarantee the other sequence is in error.

 

[Macboost]

That is an interesting approach...

Let me do some multisim work today and see what I come up with.

Thanks guys! I'll keep you updated with results

 

[Macboost]

Design complete. Tested and works.

 

[Macboost]

And... It doesn't work.