Problem with serial shift registers

[Harald Kapp]

The RC logic on the /OE input is unnecessary. You should simply connect /OE to GND.
If you want to reset the shift registers at power on, you should use the /SRCLR input (pin 10). Also, using an RC combination alone is not a very good idea. Use at least a Schmitt-Trigger to condition the slow edge from the RC circuit into a clear logic signal or use a small reset controller like e.g. the TL7705A.
What is completely unclear from your diagram is how you use the clock inputs. The 74HC595 has two clock inputs:

• SRCLK
• RCLK

The typical application would use SRCLK to shift data into the shift register. Then when all data has bee set up in the shift register, use RCLK to transfer the data into the output register with a single pulse. This way you will not see how the data shifts through the register, only the final value will appear at the output. I think you may have connected SRCLK and RCLK, but that will have (possibly unexpected) consequences: You will need one additional clock to transfer all data into the output register or, as the datasheet states (footnote 1, page 7):

1) This set-up time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case the shift register is one clock pulse ahead of the storage register.

 

[Anard]

No, I use "Clock" and "ChipSelect", which is less confusing for (respectively) SRCLK and RCLK.
So, in software, I use it as other SPI device, it's updated just when all data have been tranfered :

#define interface_rx()    Interface_Exchange8bit(uint8_t data)
#define interface_tx(Data)    Interface_Exchange8bit(Data)
#define spi_buff         SSP1BUF
#define spi_bufFull      SSP1STATbits.BF

uint8_t Interface_Exchange8bit(uint8_t data) {
   spi_buff = data;
   while (!spi_bufFull);
   return (spi_buff);
}

// Software first prepare a table arrOuts[7] containing outputs to each Shift register
void Out_Refresh(void) {
   signed char iOutGroup;
 
   Out_CS = 0;
   // shift data into shift registers
   for (iOutGroup = 6; iOutGroup >= 0; iOutGroup--)
         interface_tx(arrOuts[iOutGroup]);

   // transfer data to outputs by the rising edge of RCLK
   Out_CS = 1;
}

 

[Anard]

Hi.

Still searching for the issue, I'm totally desperate about finding a solution.
Being a newbie on electronics, I feel that my logical is improper and that I'm not looking in the right way.
Here are the facts.
Shematic is the same than previous one.

Previously, I had errors on the outputs of left-side shift registers. It was because I used OutEnable pins of drivers (74HC244) linked to ChipSelect pins of serial registers (RCLK of 74HC595).
So shift registers received high impedance signals which generated output errors in some conditions.
Following your advice, I tied OE pins from drivers to GND and it worked much better.

I made a first test after the first change, made on left side of the shematic for seeing the difference.
The improvement was immediately obvious. But I noted that the last shift register (in serie, so the top-right one) stopped working after using it a few time (it had never happened before this).
I say "after using it a few time" cause it occurs after setting some outputs of this shift register, but not always with the same output. It's as if this last chip encountered a fault which put it in security mode.
It always goes back to work after shutting down and rebooting system.

I finished the modification (by tying OE pin of the right driver to GND) to see if it could solve this new trouble.
But not.

OE pins of shift registers were tied to about 0.4V with a delay given by a RC timer, which let me the time to initialize outputs in software during boot time. You said me that it'd be better to pass through a Schmitt trigger.
So I made the same RC timer on the fourth pin of driver which now send a clean 0/5V to shift registers. It was easier than using CLR pin of shift registers but I agree it would be better for future circuits.
Still no improvement.

For me, it's an evidence I made a short-circuit anywere when modifying left-side driver's circuit cause it's when the problem appeared.
But how could it be possible that it have just effect on the very last shift register ? I feel it impossible.
So I mainly find for problems near the "ill" chip. I tried replacing it by a new one, replacing closest driver by a new one and disconnecting shift register from its output (to avoid its eventually negative effect).
With no result.

Do you think it could be a software error ? I dont believe it cause the issue would be always visible, even on startup. Moreover I don't remember having edited it before the problem appeared.

If you had a idea about which conditions could put this chip in error, I could try to search from these ways... but I've no idea about this. I thought about a bad connection on its decoupling capacitor (100nF) but it seems all OK.

So sorry for my english, especially technical. Nevertheless, I hope you could understand my query.
Thanks so much for your help.

 

[Anard]

Found ! It was a software mistake.

To prevent too much consumption, software stops activating shift register outputs when 6 of them are opened (it controls a ULN2803 which may draw too much current if more than 6 outputs are enabled together).
For a fu..ing ridiculous mistake from myself, in some conditions, the variable which indicates how much outputs are enabled wasn't resetted for the last shift register !

It's all OK. Thanks again for trying to help me.

 

[Harald Kapp]

Glad you found the mistake. I would have been at a loss with respect to the hardware setup.