Nobody said:
Agreed. The question is, given that the capacitor feeds the coil, and the
HV feeds the capacitor, how to prevent the HV feeding the coil? The
resistor can't be any higher if the capacitor is to recharge fully.
You could switch the HV off with e.g. a FET during the on state, but that
requires a transformer or a high-side driver. If you're going to that
level, it's getting to the point where you may as well go the whole hog
and use an H-bridge, which lets you recover the energy stored in the coil
on switch-off to use for the next switch-on.
I like the simplicity of the previous circuit charging the cap
via R1.
FIG. 1
======
R1
4.7K / 5W
+120v >---\/\/\-----o-----------o-----o-------.
| | | |_
D1 | [R2] [C2] _) L1
+4v >----|>|------o [10k] [1uF] _)
| | | _) (4H, 55ohms)
| '--o--' |
--- C1 | D2 |
--- 1uF '----|<|---o
| |
| | |--'
=== | |<-. Q1
_____| |--+
|
===
GND
The only way to reduce that dissipation is to replace
R1 with a switching element.
I gave such a scheme in block form up above--it's a lot
busier. But, if you're dead-set on saving dissipation,
that's what needs doing.
Here's one possible sketch:
FIG. 2
======
D1
.--------------|<|---------------------.
| Q1 |
+120v >-----o-----o----. .-----o-------. |
| e \ / c | | |
[R1] ----- - | |
| | b ^ D2 | |
'-------o - _) L1 |
| | _) 4H / |
DATA+ >--. | === _) 55r |
| [R2] GND | |
| | | |
.-----o----o-----[R3]---|--------. | |
| | | | | | |
| | | |/ Q2 | o-------'
| | | +5v---| MPSA42 | |
| [R4] | |>. | |
| | | | | |
| | | __ [R5] | |
| | '--| \ | | |
| | | )O----o | |
| o-------|__/ | | |
| | 74HC132 | | |
| | | | |
[R6] \| Q3 | | |/ Q4
| |---------------|--------o-----| MPSA42
| .<| | |>.
| | | |
o-----o------[R8]-------' [R9]
| |
[R7] ===
| GND
===
GND
This is a hysteretic buck. Q1 is the switch, current is
sensed across R9, and Q3 is the comparator. R6-7 sets
the current limit as a fraction of the DATA+ signal input,
while R8 provides hysteresis.
When the current in R9 is below setpoint, Q3 is biased off
by R6-8, both 'HC132 inputs are high, driving the output
low, and switch Q1 is on. When i(L1) reaches the setpoint,
Q3's base rises until it conducts, 'HC132 output goes high,
Q1 cuts off, and L1 freewheels efficiently through D2 and Q4.
When DATA+ goes low, Q4 turns off and the inductor flies
back, returning its energy to the +120v supply.
The currents are small, so D1-2 are signal diodes and
snubbing is probably unnecessary.
The DATA+ signal could also serve as the +5V supply
powering the logic gate.
The whole should draw roughly 3 or 4 mA from the +120v.
Cheers,
James Arthur