NE555 R-S bistable IC

[Integrator741]

Hello guys,

I need your help to understand whats happening inside R-S bistable part of NE555 chip.

Is it simple Cross-coupled NAND gates or something else?

Because if it would be cross-coupled nand gates the chip would have two outputs right? or am i too ignorant and I missed out something...?!

Thanks.

 

[jpanhalt]

Note that when the output is low, the discharge capacitor is ON to discharge the timing capacitor. So, there are two, complementary outputs from the flip-flop.



John

 

[Harald Kapp]

Have a look at this kit. It includes complete internal schematics.

 

[jpanhalt]

What a fun way to waste some time.

Along the same line of fun but useless, I have occasionally suggested to individuals who were desperate for a FYP that they program a 12F6xx chip to emulate the 555. Of course, the power pins are reversed. HighTechChips, Inc. (http://www.hightechips.com/ ) has already done some of that work.

That kit you link to led me to revisit my 555 folder, and I came across this drawing:


It shows the flip-flop in vivid color. The source was a web page created by Glen Williamson of the School of Engineering at North Carolina State University. Unfortunately, I couldn't find the actual link any longer and hope that credit is sufficient.

John