I don't know anything about VHDL or Verilog, the nature of being a one man band
company is that you use the easiest and cheapest tools. But can't these fancy
tools operate at the lowest simple non abstracted logic equation levels too,
excepting the actual specifing of individual fuses?
I dunno about fuses, I use Icarus verilog in Linux, and xilinx webpack in
windows.
It seems to also be able to run in Linux wine, but something screwd up in
the editor in my case.
Verilog is a HDL hardware description language, and you can construct
you logic with it in the form of gates of cause.
Make modules, compare that to little circuits, connect these etc..
If you use verilog in something like webpack, what is free, then it
knows such things as gates, registers, io buffers, blockram in the xilinx
FPGAs.
Verilog is simple, but when programming in Verilog (or VHDL) you MUST
remmeber that things happen at the same time.
So not the sequential coding as in a normal programming language, you
are more specifying circuits, the circuits are connected...
You specify input and output, one or more clocks, you can run a simultion,
print out waveforms generated, you need to specify delays.
The software will then take your circuit and map it for example to real
gates (and more complex logic modules) in a FPGA.
Verilog syntax reminds a bit of C syntax, but that is where it ends really.
Programs like webpack also let you enter diagrams, and synthesize that.
In fact there is a whole library of logic stuff, all sorts of flipflops,
shift registers, buffers, quite a bit, but things may not always do what
you expect.
As hardware guy you will perhaps get faster started then as software
guy with HDL.
JP
