JFet Source Follower Biasing issues

[Stretto]

The following is a simple JFET source follower amplifier:

http://imageshack.us/photo/my-images/220/jfetsourcefollower.png/

Every combination of the switches work as expected. When I mock up this
circuit it does not work for direct coupling to any degree like the
simulation. The main issue is when the low side of the AC source is
connected to VDD. In this case I'd expect the DC bias point to be 5V. When
it is instead grounded the DC bias point depends on the R2, R3, and R4.

Choosing R4 << R3 = R2 sets the bias point at 2.5V which can be remedied by
using Vdd = 10V.

The real question is why does my source no behave like the simulation. I'm
using the output of the sound card and cannot "lift" it's ground to work in
any significant way. (I guess the sound cards output is capacitively coupled
but that should then not change anything.

What I'd like to do is direct couple a jfet source follower with output bias
Vcc/2. While I don't have any problem getting this in simulation I can't get
my circuit to work(works find using capacitive coupling).

The only thing I can think of is that it has something to do with the source
circuit itself. It's not passing the DC like it does in the simulation.

Any ideas?

 

[Stretto]

wrote in message

The following is a simple JFET source follower amplifier:

http://imageshack.us/photo/my-images/220/jfetsourcefollower.png/

Every combination of the switches work as expected. When I mock up this
circuit it does not work for direct coupling to any degree like the
simulation. The main issue is when the low side of the AC source is
connected to VDD. In this case I'd expect the DC bias point to be 5V. When
it is instead grounded the DC bias point depends on the R2, R3, and R4.

Choosing R4 << R3 = R2 sets the bias point at 2.5V which can be remedied
by
using Vdd = 10V.

The real question is why does my source no behave like the simulation. I'm
using the output of the sound card and cannot "lift" it's ground to work
in
any significant way. (I guess the sound cards output is capacitively
coupled
but that should then not change anything.

What I'd like to do is direct couple a jfet source follower with output
bias
Vcc/2. While I don't have any problem getting this in simulation I can't
get
my circuit to work(works find using capacitive coupling).

The only thing I can think of is that it has something to do with the
source
circuit itself. It's not passing the DC like it does in the simulation.

Any ideas?

What you really want is the source voltage to equal the gate voltage.
This is hard to do with a Jfet because the IDSS is all over the map.
Further, you are modulating this current with the swing of the fet
since the voltage across the resistor R1 is varying with the source.
This adds distortion to the buffer. Now if you are building one buffer
and can tweak it, I'd substitute a current source pulling on the
source of the fet. It would have to be variable to cover the range of
IDSS. If you pull some current equal to the IDSS of the fet, then the
VGS will be zero. You could connect directly to the gate of the jfet,
assuming the signal driving the jfet isn't cap coupled.

-----------

It doesn't have to be exactly but ideally from what I read a an ideal jfet
has VGS = 0. I'm am seeing this behavior from what I remember but simply
getting the gate voltage to be biased properly is the problem. It may not be
an issue with the jfet at all but an issue with the source.

I assuming you mean that I have to pull off enough current to zero Vgs which
will have to do with rs. rs is ~= 50 ohms for the jfet I have(if using a dmm
is of any use measuring it) and my source resistor is on the order of 100k.
So whatever variations won't matter much. I don't need perfect matching at
this point.

I do not know if the source is CC'ed or not. I assume it is for the sound
card but it will not always be.