JFET Common Source DC Amplifier Temperature Compensation

[D from BC]

Jim Thompson a écrit :

Fred Bartoli >
Jim Thompson a écrit :
D from BC wrote:

[snip]
Except for the "sweet spot" bias condition, gain (small signal)
and output Q-point probably vary independently.

Are you sure that they are independent?
For a given jfet model gm is strongly linked to the drain current
(and essentially free from IDSS).

They're not "independent", but I don't think incremental gain
and bias Q-point will exactly track.

Ah, a bit of french meaning slept in there.

Now you said they'd probably vary independently, which they don't
(for ex.http://www.alldatasheet.com/view.jsp?Searchword=2SK170).

But gain and bias point sure can't exactly track. For this to be
so, you'd have to have gm proportional to Id, which you can't
ignore to be the hallmark of exponential

Well, as I understand it, and based on my measurements as well,
gm does mostly track Id, more or less independent of Idss,
especially at currents well below Idss. But I don't get the Q
discussion y'all are having here. To my mind the Id operating
point is best set independently from the particular miserable
JFET's Vgs vs. Id, etc. I mean, part-to-part, sheesh! Bummer!

But anyway, whatever, I suggest that D just go ahead and use a
JFET opamp. I mean, I'm a "big" fan of JFETs and use them as I
can, for when they're best, but what an unholy pain they are!

Well..If I've posted anything goofy about JFET's, it's probably
because I've forgotten them.
I usually dodge discrete transistors and use op amps instead.
But..this time around, a JFET looked like a good fit.

It did the following:
Low noise
Impedance transformation
Level shifting
Below rail small signal amplification
Fast
small footprint
cheap

I have no idea how drify a JFET can be...
I just know that generally all transistors change with temperature.

I might go to an op amp solution just to avoid all the textbook
reading..


D from BC

 

[D from BC]

My app uses a JFET..

What are some ways to temperature compensate a common source JFET DC
amplifier.

Vdd=5V
|
10K
|
+------------Vout (biased for 50% Vdd)
|d
signal--->[ N JFET
|s
|
Gnd

'DC' amplifier.

Details:
1) The signal does contain a stable bias voltage.
2) Temp range: 20C to 50C
3) Vout thermal error of +/-10mVdc.
4) BW: DC to 2Mhz

I'm guessing compensation by:
1) PTC or NTC resistor
2) Use another JFET and feed in anti drift.

That would be my avenue. There are duals such as this one, pretty low noise:
http://www.semicon.toshiba.co.jp/docs/datasheet/en/Transistor/2SK3320_en_datasheet_071101.pdf

Buying those might be a challenge though.

3) Find a special jfet (IC??) << not an op amp!

Possible ??

Available from Digikey
Nearly 3000 in stock..
Two N JFETS in one package
http://www.nxp.com/acrobat_download/datasheets/PMBFJ620_1.pdf


D from BC

 

[Fred Bartoli]

Winfield a écrit :

Jim Thompson a écrit :

Fred Bartoli >
Jim Thompson a écrit :
D from BC wrote:
[snip]
Except for the "sweet spot" bias condition, gain (small signal)
and output Q-point probably vary independently.
Are you sure that they are independent?
For a given jfet model gm is strongly linked to the drain current
(and essentially free from IDSS).
They're not "independent", but I don't think incremental gain
and bias Q-point will exactly track.

Ah, a bit of french meaning slept in there.

Now you said they'd probably vary independently, which they don't
(for ex.http://www.alldatasheet.com/view.jsp?Searchword=2SK170).

But gain and bias point sure can't exactly track. For this to be
so, you'd have to have gm proportional to Id, which you can't
ignore to be the hallmark of exponential

Well, as I understand it, and based on my measurements as well,
gm does mostly track Id, more or less independent of Idss,
especially at currents well below Idss. But I don't get the Q
discussion y'all are having here. To my mind the Id operating
point is best set independently from the particular miserable
JFET's Vgs vs. Id, etc. I mean, part-to-part, sheesh! Bummer!

I'm not arguing about "Q point". Just about gm dependency on Id.
I totally agree about the almost non dependency of gm on Idss and that
gm is mostly tied to Id for a given fet model (hence biasing is best
done by setting Id).
But gm doesn't track Id. I mean gm isn't proportionnal to Id, but rather
to sqrt(Id). Ok at very low current in the subthreshold region Id
becomes exponential, but this isn't the usual way of using jfets,
specially when we want low noise.

 

[RRogers]

My app uses a JFET..

What are some ways to temperature compensate a common source JFET DC
amplifier.

Vdd=5V
|
10K
|
+------------Vout (biased for 50% Vdd)
|d
signal--->[ N JFET
|s
|
Gnd

'DC' amplifier.

Details:
1) The signal does contain a stable bias voltage.
2) Temp range: 20C to 50C
3) Vout thermal error of +/-10mVdc.
4) BW: DC to 2Mhz

I'm guessing compensation by:
1) PTC or NTC resistor
2) Use another JFET and feed in anti drift.
3) Find a special jfet (IC??) << not an op amp!

Possible ??

D from BC

As I recall, you can stabilize the bias point by a source resistance
network providing a specific impedance at a specific voltage using a
Thevenin equivalent divider. I don't have time right now, but if you
need I will figure it out later. The match is accurate not needing
PTC or NTC; just matching one curve against another. Junction
threshold shift vs. mho's as I recall. It's been 40 years so the
memory has faded; actually 6 months is starting to be a stretch

RRogers

 

[Vladimir Vassilevsky]

What are some ways to temperature compensate a common source JFET DC
amplifier.

Vdd=5V
|
10K
|
+------------Vout (biased for 50% Vdd)
|d
signal--->[ N JFET
|s
|
Gnd

Here is an incredibly complex schematics:

http://www.abvolt.com/misc/jfet_.gif

Is it clear? Just watch for the dominant pole and don't forget the Ohm's
law.


Vladimir Vassilevsky
DSP and Mixed Signal Design Consultant
http://www.abvolt.com

 

[Joerg]

On Mon, 19 Nov 2007 16:27:11 -0700, Jim Thompson

On Mon, 19 Nov 2007 15:14:30 -0800, D from BC

On Mon, 19 Nov 2007 15:25:09 -0700, Jim Thompson

On Mon, 19 Nov 2007 14:01:55 -0800, D from BC

My app uses a JFET..
What are some ways to temperature compensate a common source JFET DC
amplifier.

Vdd=5V
|
10K
|
+------------Vout (biased for 50% Vdd)
|d
signal--->[ N JFET |s
|
Gnd

'DC' amplifier.
Details: 1) The signal does contain a stable bias voltage.
2) Temp range: 20C to 50C 3) Vout thermal error of +/-10mVdc.
4) BW: DC to 2Mhz

I'm guessing compensation by:
1) PTC or NTC resistor
2) Use another JFET and feed in anti drift.
3) Find a special jfet (IC??) << not an op amp!

Possible ??


D from BC
What does "temperature compensate" mean? Bias point, gain, both?

...Jim Thompson
Let's say the gate voltage is set for Vout = 2.5V...
Vout can vary with temperature..Especially with no JFET source
resistor.

For a DC amplifier like this, doesn't DC bias thermal drift at the
output also look like DC gain thermal drift?

IIRC the power supply drifting with temperature can cause bias drift
alone.


D from BC
Except for the "sweet spot" bias condition, gain (small signal) and
output Q-point probably vary independently.

Instead of your vague "specification" what is it you are trying to
accomplish?

...Jim Thompson

Ahhh... I think you've caught on that I dumb down problems to the
point of making it the wrong problem

Gee...I dunno if I can devague it more...
I'll try...
I need a fast DC amplifier with an input range of 0 to
-200mV(negative) with a response up to 2Mhz.
The output of the amplifier has to reach 2.5V out for -200mV in.
There is no negative supply present.

I thought a JFET would be best..but spoiled by thermal drift.....
My alternatives were:
Use resistive network + op amp Create a negative supply + op amp
Put one of those 'beyond the rails' op amps to the test.

Many regular opamps can work down to about 300mV below the negative
rail but you'd have to find one that's fast enough and low enough in
offset.

Negative rail IC + op amp

If you have a spare inverter somewhere you could make in inverting
switcher.

How about an ordinary single-supply op amp wired as an inverter? Ground
the noninverting input, and bob's your uncle.

If his source can stomach the current, yes. But then he'd better make
sure it can operate properly with the input at the negative rail. Most
of those are ok a few hundred mV below, at least the older one.

 

[Joerg]

My app uses a JFET..

What are some ways to temperature compensate a common source JFET DC
amplifier.

Vdd=5V
|
10K
|
+------------Vout (biased for 50% Vdd)
|d
signal--->[ N JFET
|s
|
Gnd

'DC' amplifier.

Details:
1) The signal does contain a stable bias voltage.
2) Temp range: 20C to 50C
3) Vout thermal error of +/-10mVdc.
4) BW: DC to 2Mhz

I'm guessing compensation by:
1) PTC or NTC resistor
2) Use another JFET and feed in anti drift.

That would be my avenue. There are duals such as this one, pretty low noise:
http://www.semicon.toshiba.co.jp/docs/datasheet/en/Transistor/2SK3320_en_datasheet_071101.pdf

Buying those might be a challenge though.

3) Find a special jfet (IC??) << not an op amp!

Possible ??

Available from Digikey
Nearly 3000 in stock..
Two N JFETS in one package
http://www.nxp.com/acrobat_download/datasheets/PMBFJ620_1.pdf

Nice! Not exactly a bargain and a bit noisy for my taste but those
should be really practical when you have to temperature-gang something.

 

[Joerg]

Jim Thompson a écrit :
Fred Bartoli >
Jim Thompson a écrit :
D from BC wrote:
[snip]
Except for the "sweet spot" bias condition, gain (small signal)
and output Q-point probably vary independently.
Are you sure that they are independent?
For a given jfet model gm is strongly linked to the drain current
(and essentially free from IDSS).
They're not "independent", but I don't think incremental gain
and bias Q-point will exactly track.
Ah, a bit of french meaning slept in there.

Now you said they'd probably vary independently, which they don't
(for ex.http://www.alldatasheet.com/view.jsp?Searchword=2SK170).

But gain and bias point sure can't exactly track. For this to be
so, you'd have to have gm proportional to Id, which you can't
ignore to be the hallmark of exponential

Well, as I understand it, and based on my measurements as well,
gm does mostly track Id, more or less independent of Idss,
especially at currents well below Idss. But I don't get the Q
discussion y'all are having here. To my mind the Id operating
point is best set independently from the particular miserable
JFET's Vgs vs. Id, etc. I mean, part-to-part, sheesh! Bummer!

But anyway, whatever, I suggest that D just go ahead and use a
JFET opamp. I mean, I'm a "big" fan of JFETs and use them as I
can, for when they're best, but what an unholy pain they are!

Well..If I've posted anything goofy about JFET's, it's probably
because I've forgotten them.
I usually dodge discrete transistors and use op amps instead.
But..this time around, a JFET looked like a good fit.

It did the following:
Low noise

Be sure to check that close to DC. RF JFET can be rather noisy down there.

Impedance transformation
Level shifting
Below rail small signal amplification
Fast
small footprint

Not many of them have been ported to SC75 though. That would be sweet.

cheap

Yes!


I have no idea how drify a JFET can be...
I just know that generally all transistors change with temperature.

Check figure 10 here:

http://www.colorado.edu/physics/phys3330/phys3330_fa07/pdfdocs/AN102FETbiasing.pdf

The IMHO biggest issue with JFETs is the large production spread. That's
where arrays can come in handy.

I might go to an op amp solution just to avoid all the textbook
reading..

Among mass product designers that would be considered taking the chicken
exit ;-)

 

[John Larkin]

Fred Bartoli wrote:
Jim Thompson a écrit :
Fred Bartoli >
Jim Thompson a écrit :
D from BC wrote:
[snip]
Except for the "sweet spot" bias condition, gain (small signal)
and output Q-point probably vary independently.
Are you sure that they are independent?
For a given jfet model gm is strongly linked to the drain current
(and essentially free from IDSS).
They're not "independent", but I don't think incremental gain
and bias Q-point will exactly track.
Ah, a bit of french meaning slept in there.

Now you said they'd probably vary independently, which they don't
(for ex.http://www.alldatasheet.com/view.jsp?Searchword=2SK170).

But gain and bias point sure can't exactly track. For this to be
so, you'd have to have gm proportional to Id, which you can't
ignore to be the hallmark of exponential
Well, as I understand it, and based on my measurements as well,
gm does mostly track Id, more or less independent of Idss,
especially at currents well below Idss. But I don't get the Q
discussion y'all are having here. To my mind the Id operating
point is best set independently from the particular miserable
JFET's Vgs vs. Id, etc. I mean, part-to-part, sheesh! Bummer!

But anyway, whatever, I suggest that D just go ahead and use a
JFET opamp. I mean, I'm a "big" fan of JFETs and use them as I
can, for when they're best, but what an unholy pain they are!

Well..If I've posted anything goofy about JFET's, it's probably
because I've forgotten them.
I usually dodge discrete transistors and use op amps instead.
But..this time around, a JFET looked like a good fit.

It did the following:
Low noise

Be sure to check that close to DC. RF JFET can be rather noisy down there.

GaAs fets can have nf's in the 0.5 dB range at rf, but be ghastly at
low frequencies. Even the Gm can go to hell below a couple of hundred
khz.

John

 

[RST Engineering \(jw\)]

I'm sure you are correct by experience, and I've never wasted money on an RF
gasfet and used it at lf so I can't argue from experience either.

I'd be interested in some explanation of what you observed to be true. I
can't think of any mechanism that honks up a gasfet at low freq ... it's not
like they internally matched it to optimize its rf response, or is that the
hiccup?

Jim

 

[Winfield Hill]

Winfield a écrit :

Jim Thompson a écrit :
Fred Bartoli >
Jim Thompson a écrit :
D from BC wrote:
[snip]
Except for the "sweet spot" bias condition, gain (small signal)
and output Q-point probably vary independently.
Are you sure that they are independent?
For a given jfet model gm is strongly linked to the drain current
(and essentially free from IDSS).
They're not "independent", but I don't think incremental gain
and bias Q-point will exactly track.
Ah, a bit of french meaning slept in there.
Now you said they'd probably vary independently, which they don't
(for ex.http://www.alldatasheet.com/view.jsp?Searchword=2SK170).
But gain and bias point sure can't exactly track. For this to be
so, you'd have to have gm proportional to Id, which you can't
ignore to be the hallmark of exponential

Well, as I understand it, and based on my measurements as well,
gm does mostly track Id, more or less independent of Idss,
especially at currents well below Idss. But I don't get the Q
discussion y'all are having here. To my mind the Id operating
point is best set independently from the particular miserable
JFET's Vgs vs. Id, etc. I mean, part-to-part, sheesh! Bummer!

I'm not arguing about "Q point". Just about gm dependency on Id.
I totally agree about the almost non dependency of gm on Idss and that
gm is mostly tied to Id for a given fet model (hence biasing is best
done by setting Id).
But gm doesn't track Id. I mean gm isn't proportionnal to Id, but rather
to sqrt(Id). Ok at very low current in the subthreshold region Id
becomes exponential, but this isn't the usual way of using jfets,
specially when we want low noise.

Yes, Fred, thanks, when I say track Id, I am thinking
of low currents, because I'm usually using large-die
parts, with 500mA Idss, etc., at "low" currents like
5mA, etc., where they act more like BJT transistors,
with Id vs Vgs exponential, as you say, and gm ~ Id.
I'd better not go further out on the proverbial limb,
not having my measured data in front of me.

 

[D from BC]

What are some ways to temperature compensate a common source JFET DC
amplifier.

Vdd=5V
|
10K
|
+------------Vout (biased for 50% Vdd)
|d
signal--->[ N JFET
|s
|
Gnd

Here is an incredibly complex schematics:

http://www.abvolt.com/misc/jfet_.gif

Is it clear? Just watch for the dominant pole and don't forget the Ohm's
law.


Vladimir Vassilevsky
DSP and Mixed Signal Design Consultant
http://www.abvolt.com

That's like the circuit I thought up..
I just went above not below...if that makes sense..

http://www.members.shaw.ca/chainsaw/SED/JFETamp.jpg
613Kb LTSpice screen capture
Attempt at JFET anti-thermal drift.

Yeah...it keeps the bias level steady, but it cannot distinguish
between thermal drift and plain DC.
So..it's not a DC amp and the circuit acts like the electronic
equivalent of a coupling capacitor.

The nice part of my circuit is that J1 is 'untouched'. No parasitics
introduced. The JFET can be 'garnished' with reactive components as
used in RF techniques.

I think if I were to put a negative reference voltage on the J2 gate,
that would make J1 thermally stable only when Vin = VgJ2.
Which..in my app...would be ok..

But..I think it gets uglier.... I need a thermally stable negative
reference.


D from BC

 

[D from BC]

Fred Bartoli wrote:
Jim Thompson a écrit :
Fred Bartoli >
Jim Thompson a écrit :
D from BC wrote:
[snip]
Except for the "sweet spot" bias condition, gain (small signal)
and output Q-point probably vary independently.
Are you sure that they are independent?
For a given jfet model gm is strongly linked to the drain current
(and essentially free from IDSS).
They're not "independent", but I don't think incremental gain
and bias Q-point will exactly track.
Ah, a bit of french meaning slept in there.

Now you said they'd probably vary independently, which they don't
(for ex.http://www.alldatasheet.com/view.jsp?Searchword=2SK170).

But gain and bias point sure can't exactly track. For this to be
so, you'd have to have gm proportional to Id, which you can't
ignore to be the hallmark of exponential
Well, as I understand it, and based on my measurements as well,
gm does mostly track Id, more or less independent of Idss,
especially at currents well below Idss. But I don't get the Q
discussion y'all are having here. To my mind the Id operating
point is best set independently from the particular miserable
JFET's Vgs vs. Id, etc. I mean, part-to-part, sheesh! Bummer!

But anyway, whatever, I suggest that D just go ahead and use a
JFET opamp. I mean, I'm a "big" fan of JFETs and use them as I
can, for when they're best, but what an unholy pain they are!

Well..If I've posted anything goofy about JFET's, it's probably
because I've forgotten them.
I usually dodge discrete transistors and use op amps instead.
But..this time around, a JFET looked like a good fit.

It did the following:
Low noise

Be sure to check that close to DC. RF JFET can be rather noisy down there.

Impedance transformation
Level shifting
Below rail small signal amplification
Fast
small footprint

Not many of them have been ported to SC75 though. That would be sweet.

cheap

Yes!


I have no idea how drify a JFET can be...
I just know that generally all transistors change with temperature.

Check figure 10 here:

http://www.colorado.edu/physics/phys3330/phys3330_fa07/pdfdocs/AN102FETbiasing.pdf

The IMHO biggest issue with JFETs is the large production spread. That's
where arrays can come in handy.

I might go to an op amp solution just to avoid all the textbook
reading..

Among mass product designers that would be considered taking the chicken
exit ;-)

Thanks for the link...that's a good read...
On
http://www.colorado.edu/physics/phys3330/phys3330_fa07/pdfdocs/AN102FETbiasing.pdf
p. 4

"The self-bias scheme is a reasonable choice for single ended dc
amplifiers and for ac amplifiers. In unbypassed or dc circuits, some
compromise must be made between the gain loss due to current feedback
degeneration and the advantage of current stabilization achieved with
high Rs"

Translation:
For a DC JFET app, gain is traded off for thermal stability when using
Rs.

I'm proposing a 'no compromise' JFET DC amp. No Rs! Maximum DC gain
with thermal comp..

If that's possible...


D from BC

 

[Joerg]

On Mon, 19 Nov 2007 19:07:30 -0800 (PST), Winfield

Fred Bartoli wrote:
Jim Thompson a écrit :
Fred Bartoli >
Jim Thompson a écrit :
D from BC wrote:
[snip]
Except for the "sweet spot" bias condition, gain (small signal)
and output Q-point probably vary independently.
Are you sure that they are independent?
For a given jfet model gm is strongly linked to the drain current
(and essentially free from IDSS).
They're not "independent", but I don't think incremental gain
and bias Q-point will exactly track.
Ah, a bit of french meaning slept in there.

Now you said they'd probably vary independently, which they don't
(for ex.http://www.alldatasheet.com/view.jsp?Searchword=2SK170).

But gain and bias point sure can't exactly track. For this to be
so, you'd have to have gm proportional to Id, which you can't
ignore to be the hallmark of exponential
Well, as I understand it, and based on my measurements as well,
gm does mostly track Id, more or less independent of Idss,
especially at currents well below Idss. But I don't get the Q
discussion y'all are having here. To my mind the Id operating
point is best set independently from the particular miserable
JFET's Vgs vs. Id, etc. I mean, part-to-part, sheesh! Bummer!

But anyway, whatever, I suggest that D just go ahead and use a
JFET opamp. I mean, I'm a "big" fan of JFETs and use them as I
can, for when they're best, but what an unholy pain they are!
Well..If I've posted anything goofy about JFET's, it's probably
because I've forgotten them.
I usually dodge discrete transistors and use op amps instead.
But..this time around, a JFET looked like a good fit.

It did the following:
Low noise

Be sure to check that close to DC. RF JFET can be rather noisy down there.

Impedance transformation
Level shifting
Below rail small signal amplification
Fast
small footprint

Not many of them have been ported to SC75 though. That would be sweet.

cheap
Yes!


I have no idea how drify a JFET can be...
I just know that generally all transistors change with temperature.

Check figure 10 here:

http://www.colorado.edu/physics/phys3330/phys3330_fa07/pdfdocs/AN102FETbiasing.pdf

The IMHO biggest issue with JFETs is the large production spread. That's
where arrays can come in handy.

I might go to an op amp solution just to avoid all the textbook
reading..

Among mass product designers that would be considered taking the chicken
exit ;-)

Thanks for the link...that's a good read...
On
http://www.colorado.edu/physics/phys3330/phys3330_fa07/pdfdocs/AN102FETbiasing.pdf
p. 4

"The self-bias scheme is a reasonable choice for single ended dc
amplifiers and for ac amplifiers. In unbypassed or dc circuits, some
compromise must be made between the gain loss due to current feedback
degeneration and the advantage of current stabilization achieved with
high Rs"

Translation:
For a DC JFET app, gain is traded off for thermal stability when using
Rs.

I'm proposing a 'no compromise' JFET DC amp. No Rs! Maximum DC gain
with thermal comp..

If that's possible...

If you go to a company like Interfet and plop a million Dollars onto the
conference table they might be willing to run a few tightly controlled
wafers for you

 

[Jim Thompson]

My app uses a JFET..

What are some ways to temperature compensate a common source JFET DC
amplifier.

Vdd=5V
|
10K
|
+------------Vout (biased for 50% Vdd)
|d
signal--->[ N JFET
|s
|
Gnd

'DC' amplifier.

Details:
1) The signal does contain a stable bias voltage.
2) Temp range: 20C to 50C
3) Vout thermal error of +/-10mVdc.
4) BW: DC to 2Mhz

I'm guessing compensation by:
1) PTC or NTC resistor
2) Use another JFET and feed in anti drift.
3) Find a special jfet (IC??) << not an op amp!

Possible ??


D from BC

Sort of like this...

http://analog-innovations.com/SED/DfromBC-Bias.pdf

Not dead-on, but close... exact solution is left as an exercise for
the student ;-)

...Jim Thompson

 

[Vladimir Vassilevsky]

D from BC wrote:

What are some ways to temperature compensate a common source JFET DC
amplifier.

Vdd=5V
|
10K
|
+------------Vout (biased for 50% Vdd)
|d
signal--->[ N JFET
|s
|
Gnd

Here is an incredibly complex schematics:

http://www.abvolt.com/misc/jfet_.gif

Is it clear? Just watch for the dominant pole and don't forget the Ohm's
law.

Yeah...it keeps the bias level steady, but it cannot distinguish
between thermal drift and plain DC.
So..it's not a DC amp and the circuit acts like the electronic
equivalent of a coupling capacitor.

Here we go:

http://www.abvolt.com/misc/jfet2.gif

Paycheck time

Vladimir Vassilevsky
DSP and Mixed Signal Design Consultant
http://www.abvolt.com

 

[Fred Bartoli]

Winfield Hill a écrit :

Winfield a écrit :

Fred Bartoli wrote:
Jim Thompson a écrit :
Fred Bartoli >
Jim Thompson a écrit :
D from BC wrote:
[snip]
Except for the "sweet spot" bias condition, gain (small signal)
and output Q-point probably vary independently.
Are you sure that they are independent?
For a given jfet model gm is strongly linked to the drain current
(and essentially free from IDSS).
They're not "independent", but I don't think incremental gain
and bias Q-point will exactly track.
Ah, a bit of french meaning slept in there.
Now you said they'd probably vary independently, which they don't
(for ex.http://www.alldatasheet.com/view.jsp?Searchword=2SK170).
But gain and bias point sure can't exactly track. For this to be
so, you'd have to have gm proportional to Id, which you can't
ignore to be the hallmark of exponential
Well, as I understand it, and based on my measurements as well,
gm does mostly track Id, more or less independent of Idss,
especially at currents well below Idss. But I don't get the Q
discussion y'all are having here. To my mind the Id operating
point is best set independently from the particular miserable
JFET's Vgs vs. Id, etc. I mean, part-to-part, sheesh! Bummer!

I'm not arguing about "Q point". Just about gm dependency on Id.
I totally agree about the almost non dependency of gm on Idss and that
gm is mostly tied to Id for a given fet model (hence biasing is best
done by setting Id).
But gm doesn't track Id. I mean gm isn't proportionnal to Id, but rather
to sqrt(Id). Ok at very low current in the subthreshold region Id
becomes exponential, but this isn't the usual way of using jfets,
specially when we want low noise.

Yes, Fred, thanks, when I say track Id, I am thinking
of low currents, because I'm usually using large-die
parts, with 500mA Idss, etc., at "low" currents like
5mA, etc., where they act more like BJT transistors,
with Id vs Vgs exponential, as you say, and gm ~ Id.
I'd better not go further out on the proverbial limb,
not having my measured data in front of me.

Woah, 500mA IDss!
Are you speaking of jfets or depletion mosfets?
I've never seen jfets that high. Any favorite part#?

 

[Jan Panteltje]

Here we go:

http://www.abvolt.com/misc/jfet2.gif

Paycheck time

mm, that circuit simply stabilizes the output at 2.5 V.
Not at Vin + 2.5V.
No cigars.
To put it simply, any change in Vds from the lower FET, also
due to Vin, is regulated away.

 

[Joerg]

Winfield Hill a écrit :

Winfield a écrit :



Fred Bartoli wrote:
Jim Thompson a écrit :
Fred Bartoli >
Jim Thompson a écrit :
D from BC wrote:
[snip]
Except for the "sweet spot" bias condition, gain (small signal)
and output Q-point probably vary independently.
Are you sure that they are independent?
For a given jfet model gm is strongly linked to the drain current
(and essentially free from IDSS).
They're not "independent", but I don't think incremental gain
and bias Q-point will exactly track.
Ah, a bit of french meaning slept in there.
Now you said they'd probably vary independently, which they don't
(for ex.http://www.alldatasheet.com/view.jsp?Searchword=2SK170).
But gain and bias point sure can't exactly track. For this to be
so, you'd have to have gm proportional to Id, which you can't
ignore to be the hallmark of exponential
Well, as I understand it, and based on my measurements as well,
gm does mostly track Id, more or less independent of Idss,
especially at currents well below Idss. But I don't get the Q
discussion y'all are having here. To my mind the Id operating
point is best set independently from the particular miserable
JFET's Vgs vs. Id, etc. I mean, part-to-part, sheesh! Bummer!
I'm not arguing about "Q point". Just about gm dependency on Id.
I totally agree about the almost non dependency of gm on Idss and that
gm is mostly tied to Id for a given fet model (hence biasing is best
done by setting Id).
But gm doesn't track Id. I mean gm isn't proportionnal to Id, but rather
to sqrt(Id). Ok at very low current in the subthreshold region Id
becomes exponential, but this isn't the usual way of using jfets,
specially when we want low noise.

Yes, Fred, thanks, when I say track Id, I am thinking
of low currents, because I'm usually using large-die
parts, with 500mA Idss, etc., at "low" currents like
5mA, etc., where they act more like BJT transistors,
with Id vs Vgs exponential, as you say, and gm ~ Id.
I'd better not go further out on the proverbial limb,
not having my measured data in front of me.

Woah, 500mA IDss!
Are you speaking of jfets or depletion mosfets?
I've never seen jfets that high. Any favorite part#?

Oh, there used to be wonderful power JFETs. For example the P8000 and
P8002. All very short-lived and history now :-(

 

[Fred Bartoli]

Jan Panteltje a écrit :

mm, that circuit simply stabilizes the output at 2.5 V.
Not at Vin + 2.5V.
No cigars.
To put it simply, any change in Vds from the lower FET, also
due to Vin, is regulated away.

Nope, that the first transistor vds that's stabilized at 2.5V

This circuit copies the first jfet VGS to the second one (if they are
identical).