how to get ground referenced amplified V difference from high side(250VDC) shunt?

[Harry Dellamano]

Actually, my circuit above is a short-changing cheat!
It has no standing bias for the critical transistor,
Q1, and hence cannot perform to the desired bandwidth
when Iout is near 0mA. Adding a bias like the original
non-opamp BJT current-mirror circuit, boosts the parts
count to 15, exactly the same as the all-BJT circuit.

So it's a tie. Go to the trouble of finding a suitable
low-current high-side opamp and get better zero-current
accuracy without trimming. Or something like that.


high-voltage fast high-side current monitor

10.0 +250V Iout
------+------+---/\/\----+----o ---> 0 to 10mA load
| | |
/ '--+--------|---,
\ 200 | | |
/ 1% | 200 / |
| | 1% \ |
+---------|----, / +---,
| _|_ | | | | 7.5V zener
Q1 e / -|--' | _|_/ |
mpsa92 b ---< | | /_\ _|_
PNP c \__+|------+ | --- 0.1uF
| LT1783 | | | |
| '--------|---+---+---,
/ | |
\ 1k 1.0M | / 330k
/ / \ 0.5W
| Ib = 0.25 \ Ia /
| to 0.75mA / |
| | gnd
| 10.0k |
+--/\/\---, | 10.0k
| __ | +--/\/\---, 0 to +5V
'--|- \ | 10.0k | __ | out, for
| >--+--/\/\--+--|- \ | 0 to 10mA
gnd ---|+_/ | >--+------
gnd ---|+_/

Going from left to right on the bottom, call the three 10K resistors, R1,
R2, R3 and op amps U1 and U2. Remove U1and R2. Tie the open side of R1 to
ground. Remove the ground on U2 pos input and tie to the junction of R1 and
the 1k. Two less parts and a single supply op amps. Now someone will
complain of the reduced CMR of U2 with it's inputs flopping around at 1.5MHz
but only maybe 50dB is needed..
Not sure of 1.5MHz BW, Q1 has a big pole C to B.

Cheers,
Harry

 

[cbarn24050@aol.com]

Hi - I want to put a high side shunt resistor on a grounded load
(~10ma peak) that has about 250VDC across it. I then want to have a
ground referenced voltage that is the amplified difference across the
shunt with a range of about 0-5V. I would like the voltage across the
shunt to be in the low mV range. Power supplies available to me will
be the 250V, which will be noisy, 5V, and probably some sort of +-12V
analog (clean) supply. I would like to get 8b or more of resolution
from the ground referenced amplified shunt voltage signal. I would
also like this circuit to be fast. The faster the better, MHz
bandwidth at least. If this were a lower voltage I'd just do an op-amp
difference amplifier. Unfortunately, last I checked, Apex had the
market for op-amps that can handle such high voltages fairly well
cornered, and their op-amps are expensive, large, and not particularly
quick. High side current amplifiers seem to top out at about 100VDC.

So I'm trying out various ideas. My favorite right now is to put
voltage dividers on both sides of the shunt to drop the voltage down
maybe to 0-10V on both and then use an instrumentation amplifier to
amplify that voltage. For some odd reason this bothers me, but I can't
place my finger on just why.

Am I being paranoid and the instrumentation amp is a legitimate idea,
or is there a better way to do this?

Thanks!

-Michael

Download the schematic for a tek 7a13 or 7a22 to see how to do it.

 

[Winfield]

Going from left to right on the bottom, call the three 10K resistors, R1,
R2, R3 and op amps U1 and U2. Remove U1and R2. Tie the open side of R1 to
ground. Remove the ground on U2 pos input and tie to the junction of R1 and
the 1k. Two less parts and a single supply op amps. Now someone will
complain of the reduced CMR of U2 with it's inputs flopping around at 1.5MHz
but only maybe 50dB is needed..
Not sure of 1.5MHz BW, Q1 has a big pole C to B.

Yes, of course, I thought of the one-opamp difference-
amplifier solution. But if you use a dual opamp, then
it's only a one-resistor savings, and I prefer the idea
of inverting amps at high frequencies. But you're right
about the single-supply possibility when using the one
opamp approach.

 

[Winfield]

Won't the 1M squirt in an error proportional to bus voltage?

No, any 1M current through its 200-ohm resistor is mirrored
by an identical current through the other 200-ohm resistor
and Q1, inverted, and canceling the original current at the
output opamp. So the bias current speeds up Q1 but doesn't
show up at the output.

Are you trying to compensate the collector resistance of Q1?

You could take the standing-current offset bias thingie from
the zener, or better yet use a bandgap.

Yes, right, I could have made a more precise bias current
on the high-side that way, but the low side wouldn't have
known exactly what it was, for precise cancellation. The
1M-resistor current may not be precisely known, but it's
used both high-side and low-side for precise cancellation.

Actually, wait a minute, oops!, I forgot about the 10-ohm
sense resistor.

fast high-voltage high-side current monitor, r1-b

10.0 +250V Iout
------+------+---/\/\----+----o ---> 0 to 10mA load
| | |
/ '--+--------|---,
\ 200 | | |
/ 1% | 190 / |
| | 1% \ |
+---------|----, / +---,
| _|_ | | | | 7.5V zener
Q1 e / -|--' | _|_/ |
mpsa92 b ---< | | /_\ _|_
PNP c \__+|------+ | --- 0.1uF
| LT1783 | | | |
| '--------|---+---+---,
/ | |
\ 1k 1.0M | / 330k
/ / \ 0.5W
| Ib = 0.25 \ Ia /
| to 0.75mA / |
| | gnd
| 10.0k |
+--/\/\---, | 10.0k
| __ | +--/\/\---, 0 to +5V
'--|- \ | 10.0k | __ | out, for
| >--+--/\/\--+--|- \ | 0 to 10mA
gnd ---|+_/ | >--+------
gnd ---|+_/

BTW, note how easily this circuit can be modified for
600 to 650 volts, or even higher:

10.0 +650V Iout
------+------+---/\/\----+----o ---> 0 to 10mA load
| | |
/ '--+--------|---,
\ 200 | | |
/ 1% | 190 / |
| | 1% \ |
+---------|----, / +---,
| _|_ | | | | 7.5V zener
Q1 e / -|--' | _|_/ |
mpsa92 b ---< | | /_\ _|_
PNP c \__+|------+ | --- 0.1uF
| LT1783 | | | |
\ '--------|---+---+---,
/ 1k | |
\ \ 1.0M / 680k
/ Ib = 0.35 / \ 1.0
| to 0.85mA \ /
Q2 e | |
b ---------------+ gnd
c /
| \ 1.0M
| 10.0k /
+--/\/\---, | 10.0k
| __ | +--/\/\---, 0 to +5V
'--|- \ | 10.0k | __ | out, for
| >--+--/\/\--+--|- \ | 0 to 10mA
gnd ---|+_/ | >--+------
gnd ---|+_/

There is the matter of poor mpsa92 beta, so Q1 and Q2
need to be Darlington transistors.

 

[John Larkin]

No, any 1M current through its 200-ohm resistor is mirrored
by an identical current through the other 200-ohm resistor
and Q1, inverted, and canceling the original current at the
output opamp. So the bias current speeds up Q1 but doesn't
show up at the output.

Oh. They cancel. Sneaky!

John

 

[Michael]

This oughta work: (View in Courier)

. FWB REG
. +----+ +-----+
.20AC>-+ +--|~ +|---+---| |--+------------+------>Vcc
. P||S | | |+ +--+--+ | |
. R||E | | [BFC] | | |
. I||C | | | | +--|----+ |
.20AC>-+ +--|~ -|-+-+------+ | | | | ADC
. +----+ | | Vcc [RFB] +---+---+
.250DC>-----------+-+-[Rs]--+---+-|-\ | | Vcc |
. | | | >--+---|IN OUT1|-->ADOUT1
. +---------|---+-|+/ . .
. | | GND | OUT8|-->ADOUT8
. | | | | GND |
. | +--+ +---+---+
. [LOAD] | |
. | +------------+
. |
.250GND>--------------------+

Typical ADC output circuitry:

. Vcc
. |
. [R]
. |
. | OPTO
. +-+----+
. | A C|--> To logic
. | |
. | K E|--> To logic ground
. +-+----+
. |
. D
.ADOUTn>--G
. S
. |
.250DC>-----+

Note that everything except the load is running with 250VCD as its
common, so if you need to talk to the ADC you'll need to do it
through optocouplers unless you can use the same common for your
micro. Pretty dangerous if you don't know what you're doing!

No offense intended.

Hi John - no offense taken The only way to really offend me these
days is to insult my taste in beer, or maybe say that my mom wears
combat boots. Unfortunately, I really need everything to have a common
ground, including the load. If I didn't need that I would think that
just using a low side shunt resistor would be easiest, wouldn't it?

Out of curiosity - is there a reason that my instrumentation amp idea
would not work well? There'd be a little correction needed as the
resistive dividers would be pulling some current through the shunt,
but otherwise, I thought it'd be OK. I was thinking the only thing I'd
have to worry about is finding an instrumentation amp with
sufficiently low input offset voltage, but with some cleverness that
could be cancelled out.

-Michael

 

[Michael]

Actually, my circuit above is a short-changing cheat!
It has no standing bias for the critical transistor,
Q1, and hence cannot perform to the desired bandwidth
when Iout is near 0mA. Adding a bias like the original
non-opamp BJT current-mirror circuit, boosts the parts
count to 15, exactly the same as the all-BJT circuit.

So it's a tie. Go to the trouble of finding a suitable
low-current high-side opamp and get better zero-current
accuracy without trimming. Or something like that.

high-voltage fast high-side current monitor

10.0 +250V Iout
------+------+---/\/\----+----o ---> 0 to 10mA load
| | |
/ '--+--------|---,
\ 200 | | |
/ 1% | 200 / |
| | 1% \ |
+---------|----, / +---,
| _|_ | | | | 7.5V zener
Q1 e / -|--' | _|_/ |
mpsa92 b ---< | | /_\ _|_
PNP c \__+|------+ | --- 0.1uF
| LT1783 | | | |
| '--------|---+---+---,
/ | |
\ 1k 1.0M | / 330k
/ / \ 0.5W
| Ib = 0.25 \ Ia /
| to 0.75mA / |
| | gnd
| 10.0k |
+--/\/\---, | 10.0k
| __ | +--/\/\---, 0 to +5V
'--|- \ | 10.0k | __ | out, for
| >--+--/\/\--+--|- \ | 0 to 10mA
gnd ---|+_/ | >--+------
gnd ---|+_/- Hide quoted text -

Hi Winfield - sorry for the slow response - my weekend ended up being
more busy than expected. I just worked through the math for this
circuit and I really like how you worked the numbers to achieve that
nice cancellation. Very cool. One thing I'm a little unclear about: in
your drawing, are you intending for the load to be to the left or the
right of the supply voltage? I would have assumed that you'd have the
supply on one side of the shunt, and the load on the other, but in
your schematic it appears to me that the supply is between the shunt
and the load, which confuses me.

I'm going to be regulating the 250V supply (probably something along
the lines of the "High-voltage regulated supply" in Art of
Electronics, Figure 6.47). Was your intention that the circuit would
be regulated using the point marked '250V' as feedback, with current
flowing from left to right through the 10 ohm shunt? Or am I missing
something basic?

Thanks so much for your help, I really appreciate it!

-Michael

 

[Winfield]

Going from left to right on the bottom, call the three 10K resistors, R1,
R2, R3 and op amps U1 and U2. Remove U1and R2. Tie the open side of R1 to
ground. Remove the ground on U2 pos input and tie to the junction of R1 and
the 1k. Two less parts and a single supply op amps. Now someone will
complain of the reduced CMR of U2 with it's inputs flopping around at 1.5MHz
but only maybe 50dB is needed..
Not sure of 1.5MHz BW, Q1 has a big pole C to B.

Cheers,
Harry

 

[Winfield]

Winfield Hill wrote





Going from left to right on the bottom, call the three 10K resistors,
R1, R2, R3 and op amps U1 and U2. Remove U1and R2. Tie the open side of
R1 to ground. Remove the ground on U2 pos input and tie to the junction
of R1 and the 1k. Two less parts and a single supply op amps. Now
someone will complain of the reduced CMR of U2 with it's inputs flopping
around at 1.5MHz but only maybe 50dB is needed..

OK, just to complete the ASCII record.

fast high-voltage high-side current monitor, r2

10.0 +250V Iout
------+------+---/\/\----+----o ---> 0 to 10mA load
| | |
/ '--+--------|---,
\ 200 | | |
/ 1% | 190 / |
| | 1% \ |
+---------|----, / +---,
| _|_ | | | | 7.5V zener
Q1 e / -|--' | _|_/ |
mpsa92 b ---< | | /_\ _|_
PNP c \__+|------+ | --- 0.1uF
| LT1783 | | | |
\ '--------|---+---+
/ 1k | |
\ 1.0M \ / 330k
| Ib = 0.25 / \ 0.5W
| to 0.75mA \ Ia /
| | |
| ,-------------' gnd
| | 10.0k
| +---/\/\---,
| | __ | 0 to +5V out
| '--|- \ | for 0 to 10mA
| | >---+------
+-------|+_/
| 10.0k
'---/\/\/--- gnd

Not sure of 1.5MHz BW, Q1 has a big pole C to B.

Cheers,
Harry

The mpsa92 has a low Ccb = 0.5pF at 200 volts,
according to Motorola's plots, and hopefully the
LT1783 opamp is vigorously driving the base node.
Still, the G = 10k/200 = 50 stage gain incurred
by moving the 10k resistor may be a killer, as it
implies an f_T of at least 50MHz for the 'A92. To
get that high f_T we may need to further boost the
bias current, say to 1mA. And the poor opamp, with
its 1.5MHz f_T, may also fall short of the goal.
If a faster opamp can be found, that would help, it
should be a low-power type (the LT1783 takes 300uA).

Alternately, the poor mpsa92 and the opamp can be
helped with a simple cascode stage. That way we
can select a faster low-voltage transistor for Q1.


Fast high-voltage high-side current monitor, r2-a

10.0 +250V Iout
------+------+---/\/\----+----o ---> 0 to 10mA load
| | |
/ '--+--------|---,
\ 200 | | |
/ 1% | 190 / |
| | 1% \ |
+---------|----, / +---,
| LT1783_|_ | | | | 7.5V zener
Q1 e / -|--' | _|_/ |
fast b ---< | | /_\ _|_
PNP c \__+|------+ | --- 0.1uF
| | | | |
Q2 e +--------|---+---+
mpsa92 b ------' | |
c 220k \ / 330k
| Ib = 1.1 1W / \ 0.5W
| to 1.6mA \ Ia /
| | |
1k / ,-------------' gnd
\ | 10.0k
/ +---/\/\---,
| | __ | 0 to +5V out
| '--|- \ | for 0 to 10mA
| | >---+------
+-------|+_/
| 10.0k
'---/\/\/--- gnd

Considering the painful required G=50 level-translating
stage, an alternate would be to add gain with a wideband
G = 10 opamp topside before this stage. But, I suspect
that opamp will require even more current than the 1.1mA
we just dedicated to the mpsA92. I dunno, maybe my two
opamp summing-junction approach wasn't so bad after all,
because it relaxed the high-frequency gain requirement
from the 'A92 and gave it to the low-side opamps, which
can spend whatever power is needed to nail the summing-
junction impedance and help out the hard-working mpsA92.

 

[Winfield]

Oh. They cancel. Sneaky!

John

A cascode mpsA92 stage is definitely a good idea, to
further reduce the burden on Q1 and the opamp at 1MHz.
Q2 still needs to be a Darlington for good accuracy,
so that's 17 parts. But they all earn their keep.

Fast high-voltage high-side current monitor, r1-c

10.0 +250V Iout
------+------+---/\/\----+----o ---> 0 to 10mA load
| | |
/ '--+--------|---,
\ 200 | | |
/ 1% | 190 / |
| | 1% \ |
+---------|----, / +---,
| _|_ | | | | 7.5V zener
Q1 e / -|--' | _|_/ |
fast b ---< | | /_\ _|_
PNP c \__+|------+ | --- 0.1uF
| | | | |
Q2 e +--------|---+---+
mpsa92 b ------' | |
c | \
| Ib = 0.25 | Ia / 330k
| to 0.75mA / \ 0.5W
/ \ |
\ 1k 1.0M / gnd
/ |
| 10.0k |
+--/\/\---, | 10.0k
| __ | +--/\/\---, 0 to +5V
'--|- \ | 10.0k | __ | out, for
| >--+--/\/\--+--|- \ | 0 to 10mA
gnd ---|+_/ | >--+------
gnd ---|+_/

 

[Fred Bloggs]

But not creative. Goes along.

John

You're not even close, you stunted mental midget. Unfortunately, Win's
approach, although quite fun, is dated. Anyone with an ADC also has some
processing power and calibration capabilities. This means a more
intelligent approach would relax the complexity and performance
requirements of the analog kluge and compensate with a deconvolution of
the data. Even someone as dull as you could be made into a real designer
with proper training and guidance...but that's not my job.

 

[John Larkin]

You're not even close, you stunted mental midget. Unfortunately, Win's
approach, although quite fun, is dated. Anyone with an ADC also has some
processing power and calibration capabilities. This means a more
intelligent approach would relax the complexity and performance
requirements of the analog kluge and compensate with a deconvolution of
the data. Even someone as dull as you could be made into a real designer
with proper training and guidance...but that's not my job.

Show us a schematic, Fred. I'm beginning to think that you're a
circuit-design couch potato.

An ADC would have to sample at 3 MHz, realistically, to meet his
bandwidth requirement. And you'd have to isolate 10 or 12 bits of
parallel data, plus some sort of sync, or serialize it at 30+ MHz, and
isolate that. Then there's the dac at ground, and your deconvolution
thing. All that would need a lot of power and money.

Deconvolution can't cheat the Sampling Theorem.

Draw it for us, Freddie. Or is that "not my job"?


John

 

[Jim Thompson]

[snip]

You're not even close, you stunted mental midget. Unfortunately, Win's
approach, although quite fun, is dated. Anyone with an ADC also has some
processing power and calibration capabilities. This means a more
intelligent approach would relax the complexity and performance
requirements of the analog kluge and compensate with a deconvolution of
the data. Even someone as dull as you could be made into a real designer
with proper training and guidance...but that's not my job.

Show us a schematic, Fred. I'm beginning to think that you're a
circuit-design couch potato.

An ADC would have to sample at 3 MHz, realistically, to meet his
bandwidth requirement. And you'd have to isolate 10 or 12 bits of
parallel data, plus some sort of sync, or serialize it at 30+ MHz, and
isolate that. Then there's the dac at ground, and your deconvolution
thing. All that would need a lot of power and money.

Deconvolution can't cheat the Sampling Theorem.

Draw it for us, Freddie. Or is that "not my job"?


John

"Freddie" is so bitchy I'm beginning to suspect it's HER time of the
month ;-)

...Jim Thompson

 

[John Larkin]

[snip]

You're not even close, you stunted mental midget. Unfortunately, Win's
approach, although quite fun, is dated. Anyone with an ADC also has some
processing power and calibration capabilities. This means a more
intelligent approach would relax the complexity and performance
requirements of the analog kluge and compensate with a deconvolution of
the data. Even someone as dull as you could be made into a real designer
with proper training and guidance...but that's not my job.

Show us a schematic, Fred. I'm beginning to think that you're a
circuit-design couch potato.

An ADC would have to sample at 3 MHz, realistically, to meet his
bandwidth requirement. And you'd have to isolate 10 or 12 bits of
parallel data, plus some sort of sync, or serialize it at 30+ MHz, and
isolate that. Then there's the dac at ground, and your deconvolution
thing. All that would need a lot of power and money.

Deconvolution can't cheat the Sampling Theorem.

Draw it for us, Freddie. Or is that "not my job"?


John

"Freddie" is so bitchy I'm beginning to suspect it's HER time of the
month ;-)

...Jim Thompson

What do you think he does for a living? I think he may be one of those
techs who hate engineers. His "expertise" is pretty obviously google
searches.

John

 

[Spehro Pefhany]

[snip]

You're not even close, you stunted mental midget. Unfortunately, Win's
approach, although quite fun, is dated. Anyone with an ADC also has some
processing power and calibration capabilities. This means a more
intelligent approach would relax the complexity and performance
requirements of the analog kluge and compensate with a deconvolution of
the data. Even someone as dull as you could be made into a real designer
with proper training and guidance...but that's not my job.


Show us a schematic, Fred. I'm beginning to think that you're a
circuit-design couch potato.

An ADC would have to sample at 3 MHz, realistically, to meet his
bandwidth requirement. And you'd have to isolate 10 or 12 bits of
parallel data, plus some sort of sync, or serialize it at 30+ MHz, and
isolate that. Then there's the dac at ground, and your deconvolution
thing. All that would need a lot of power and money.

Deconvolution can't cheat the Sampling Theorem.

Draw it for us, Freddie. Or is that "not my job"?


John

"Freddie" is so bitchy I'm beginning to suspect it's HER time of the
month ;-)

...Jim Thompson

What do you think he does for a living? I think he may be one of those
techs who hate engineers. His "expertise" is pretty obviously google
searches.

John

He has at least four US patents to his name, and appears to have
contributed generously to the DNC. ;-)

Best regards,
Spehro Pefhany

 

[Jim Thompson]

On Mon, 10 Dec 2007 08:12:21 -0800, John Larkin

[snip]

You're not even close, you stunted mental midget. Unfortunately, Win's
approach, although quite fun, is dated. Anyone with an ADC also has some
processing power and calibration capabilities. This means a more
intelligent approach would relax the complexity and performance
requirements of the analog kluge and compensate with a deconvolution of
the data. Even someone as dull as you could be made into a real designer
with proper training and guidance...but that's not my job.


Show us a schematic, Fred. I'm beginning to think that you're a
circuit-design couch potato.

An ADC would have to sample at 3 MHz, realistically, to meet his
bandwidth requirement. And you'd have to isolate 10 or 12 bits of
parallel data, plus some sort of sync, or serialize it at 30+ MHz, and
isolate that. Then there's the dac at ground, and your deconvolution
thing. All that would need a lot of power and money.

Deconvolution can't cheat the Sampling Theorem.

Draw it for us, Freddie. Or is that "not my job"?


John


"Freddie" is so bitchy I'm beginning to suspect it's HER time of the
month ;-)

...Jim Thompson

What do you think he does for a living? I think he may be one of those
techs who hate engineers. His "expertise" is pretty obviously google
searches.

John

He has at least four US patents to his name,

Under what name?

and appears to have
contributed generously to the DNC. ;-)
Figures!


Best regards,
Spehro Pefhany

...Jim Thompson

 

[John Larkin]

On Mon, 10 Dec 2007 08:12:21 -0800, John Larkin

[snip]

You're not even close, you stunted mental midget. Unfortunately, Win's
approach, although quite fun, is dated. Anyone with an ADC also has some
processing power and calibration capabilities. This means a more
intelligent approach would relax the complexity and performance
requirements of the analog kluge and compensate with a deconvolution of
the data. Even someone as dull as you could be made into a real designer
with proper training and guidance...but that's not my job.


Show us a schematic, Fred. I'm beginning to think that you're a
circuit-design couch potato.

An ADC would have to sample at 3 MHz, realistically, to meet his
bandwidth requirement. And you'd have to isolate 10 or 12 bits of
parallel data, plus some sort of sync, or serialize it at 30+ MHz, and
isolate that. Then there's the dac at ground, and your deconvolution
thing. All that would need a lot of power and money.

Deconvolution can't cheat the Sampling Theorem.

Draw it for us, Freddie. Or is that "not my job"?


John


"Freddie" is so bitchy I'm beginning to suspect it's HER time of the
month ;-)

...Jim Thompson

What do you think he does for a living? I think he may be one of those
techs who hate engineers. His "expertise" is pretty obviously google
searches.

John

He has at least four US patents to his name, and appears to have
contributed generously to the DNC. ;-)

Best regards,
Spehro Pefhany

Well, he's said many times that he has contempt for the sort of
electronic design we do. So he's just comic-relief/punching bag here.

John

 

[Harry Dellamano]

OK, just to complete the ASCII record.

fast high-voltage high-side current monitor, r2

10.0 +250V Iout
------+------+---/\/\----+----o ---> 0 to 10mA load
| | |
/ '--+--------|---,
\ 200 | | |
/ 1% | 190 / |
| | 1% \ |
+---------|----, / +---,
| _|_ | | | | 7.5V zener
Q1 e / -|--' | _|_/ |
mpsa92 b ---< | | /_\ _|_
PNP c \__+|------+ | --- 0.1uF
| LT1783 | | | |
\ '--------|---+---+
/ 1k | |
\ 1.0M \ / 330k
| Ib = 0.25 / \ 0.5W
| to 0.75mA \ Ia /
| | |
| ,-------------' gnd
| | 10.0k
| +---/\/\---,
| | __ | 0 to +5V out
| '--|- \ | for 0 to 10mA
| | >---+------
+-------|+_/
| 10.0k
'---/\/\/--- gnd


The mpsa92 has a low Ccb = 0.5pF at 200 volts,
according to Motorola's plots, and hopefully the
LT1783 opamp is vigorously driving the base node.
Still, the G = 10k/200 = 50 stage gain incurred
by moving the 10k resistor may be a killer, as it
implies an f_T of at least 50MHz for the 'A92. To
get that high f_T we may need to further boost the
bias current, say to 1mA. And the poor opamp, with
its 1.5MHz f_T, may also fall short of the goal.
If a faster opamp can be found, that would help, it
should be a low-power type (the LT1783 takes 300uA).

Alternately, the poor mpsa92 and the opamp can be
helped with a simple cascode stage. That way we
can select a faster low-voltage transistor for Q1.


Fast high-voltage high-side current monitor, r2-a

10.0 +250V Iout
------+------+---/\/\----+----o ---> 0 to 10mA load
| | |
/ '--+--------|---,
\ 200 | | |
/ 1% | 190 / |
| | 1% \ |
+---------|----, / +---,
| LT1783_|_ | | | | 7.5V zener
Q1 e / -|--' | _|_/ |
fast b ---< | | /_\ _|_
PNP c \__+|------+ | --- 0.1uF
| | | | |
Q2 e +--------|---+---+
mpsa92 b ------' | |
c 220k \ / 330k
| Ib = 1.1 1W / \ 0.5W
| to 1.6mA \ Ia /
| | |
1k / ,-------------' gnd
\ | 10.0k
/ +---/\/\---,
| | __ | 0 to +5V out
| '--|- \ | for 0 to 10mA
| | >---+------
+-------|+_/
| 10.0k
'---/\/\/--- gnd

Considering the painful required G=50 level-translating
stage, an alternate would be to add gain with a wideband
G = 10 opamp topside before this stage. But, I suspect
that opamp will require even more current than the 1.1mA
we just dedicated to the mpsA92. I dunno, maybe my two
opamp summing-junction approach wasn't so bad after all,
because it relaxed the high-frequency gain requirement
from the 'A92 and gave it to the low-side opamps, which
can spend whatever power is needed to nail the summing-
junction impedance and help out the hard-working mpsA92.

Let's get a gain of ten out of the bottom single supply op amp, reducing
the top section gain to 5.
Change the 10k to ground to 1.0K. Change the 10K feedback to 9.90K. Add a
1.10K from the op-amp neg input to ground. Top side gain bandwidth restored.
Cheers,
Harry

 

[Winfield Hill]

Winfield wrote[ snip ]

OK, just to complete the ASCII record.

fast high-voltage high-side current monitor, r2

10.0 +250V Iout
------+------+---/\/\----+----o ---> 0 to 10mA load
| | |
/ '--+--------|---,
\ 200 | | |
/ 1% | 190 / |
| | 1% \ |
+---------|----, / +---,
| _|_ | | | | 7.5V zener
Q1 e / -|--' | _|_/ |
mpsa92 b ---< | | /_\ _|_
PNP c \__+|------+ | --- 0.1uF
| LT1783 | | | |
\ '--------|---+---+
/ 1k | |
\ 1.0M \ / 330k
| Ib = 0.25 / \ 0.5W
| to 0.75mA \ Ia /
| | |
| ,-------------' gnd
| | 10.0k
| +---/\/\---,
| | __ | 0 to +5V out
| '--|- \ | for 0 to 10mA
| | >---+------
+-------|+_/
| 10.0k
'---/\/\/--- gnd

The mpsa92 has a low Ccb = 0.5pF at 200 volts,
according to Motorola's plots, and hopefully the
LT1783 opamp is vigorously driving the base node.
Still, the G = 10k/200 = 50 stage gain incurred
by moving the 10k resistor may be a killer, as it
implies an f_T of at least 50MHz for the 'A92. To
get that high f_T we may need to further boost the
bias current, say to 1mA. And the poor opamp, with
its 1.5MHz f_T, may also fall short of the goal.
If a faster opamp can be found, that would help, it
should be a low-power type (the LT1783 takes 300uA).

Alternately, the poor mpsa92 and the opamp can be
helped with a simple cascode stage. That way we
can select a faster low-voltage transistor for Q1.

Fast high-voltage high-side current monitor, r2-a

10.0 +250V Iout
------+------+---/\/\----+----o ---> 0 to 10mA load
| | |
/ '--+--------|---,
\ 200 | | |
/ 1% | 190 / |
| | 1% \ |
+---------|----, / +---,
| LT1783_|_ | | | | 7.5V zener
Q1 e / -|--' | _|_/ |
fast b ---< | | /_\ _|_
PNP c \__+|------+ | --- 0.1uF
| | | | |
Q2 e +--------|---+---+
mpsa92 b ------' | |
c 220k \ / 330k
| Ib = 1.1 1W / \ 0.5W
| to 1.6mA \ Ia /
| | |
1k / ,-------------' gnd
\ | 10.0k
/ +---/\/\---,
| | __ | 0 to +5V out
| '--|- \ | for 0 to 10mA
| | >---+------
+-------|+_/
| 10.0k
'---/\/\/--- gnd

Considering the painful required G=50 level-translating
stage, an alternate would be to add gain with a wideband
G = 10 opamp topside before this stage. But, I suspect
that opamp will require even more current than the 1.1mA
we just dedicated to the mpsA92. I dunno, maybe my two
opamp summing-junction approach wasn't so bad after all,
because it relaxed the high-frequency gain requirement
from the 'A92 and gave it to the low-side opamps, which
can spend whatever power is needed to nail the summing-
junction impedance and help out the hard-working mpsA92.

Let's get a gain of ten out of the bottom single supply
op amp, reducing the top section gain to 5.
Change the 10k to ground to 1.0K. Change the 10K feedback
to 9.90K. Add a 1.10K from the op-amp neg input to ground.
Top side gain bandwidth restored.

Yes, that occurred to me too, good idea. 15 parts.
In light of the lower gain, I reduced Q1's bias.

Fast high-voltage high-side current monitor, r2-b

10.0 +250V Iout
------+------+---/\/\----+----o ---> 0 to 10mA load
| | |
/ '--+--------|---,
\ 200 | | |
/ 1% | 190 / |
| | 1% \ |
+---------|----, / +---,
| LT1783_|_ | | | | 7.5V zener
Q1 e / -|--' | _|_/ |
fast b ---< | | /_\ _|_
PNP c \__+|------+ | --- 0.1uF
| | | | |
Q2 e +--------|---+---+
mpsa92 b ------' | |
c 470k \ / 330k
| Ib = 0.5 0.5W / \ 0.5W
| to 1.0mA \ Ia /
| | |
1k / ,------' gnd
\ | 9.90k
/ +---/\/\---,
| 1.10k | __ | 0 to +5V out
| ,--/\/\--+--|- \ | for 0 to 10mA
| gnd | >---+------
+--------------|+_/
| 1.00k
'---/\/\/--- gnd

 

[Winfield Hill]

Hi Winfield - sorry for the slow response - my weekend ended up being
more busy than expected. I just worked through the math for this
circuit and I really like how you worked the numbers to achieve that
nice cancellation. Very cool. One thing I'm a little unclear about: in
your drawing, are you intending for the load to be to the left or the
right of the supply voltage? I would have assumed that you'd have the
supply on one side of the shunt, and the load on the other, but in
your schematic it appears to me that the supply is between the shunt
and the load, which confuses me.

I'm going to be regulating the 250V supply (probably something along
the lines of the "High-voltage regulated supply" in Art of
Electronics, Figure 6.47). Was your intention that the circuit would
be regulated using the point marked '250V' as feedback, with current
flowing from left to right through the 10 ohm shunt? Or am I missing
something basic?

Thanks so much for your help, I really appreciate it!

-Michael

Yes, in all my drawings, the supply is on the left,
and the load on the right. Sorry for the confusion!