how to get ground referenced amplified V difference from high side(250VDC) shunt?

[Winfield]

Excellent! Pretty soon we can enroll you as an apprentice IC
designer... you put your finger right on it... balance... balance...
balance... match... match... match ;-)

...Jim Thompson

Thanks, but no that'll never happen, and I'm far too
far away from the issues you deal with all the time.
First, as a discrete designer, I'm always suffering
from a parts budget that's far too meager- it costs
too much to design in all the parts I'd like to have,
so I'm always cutting here and cutting there, leaving
out transistors and parts that would help the design
along. Second, your world is full of understanding
IC fab processes, and modeling same. That's a world
we discrete designers see very little of. Matching?
That's the IC designer's and the fab manufacturer's
responsibility. And marketing's specsmanship game.

 

[Jonathan Kirwan]

I copied the drawing below, for reference.

. +250V Rs 10.0 Iout
. IN ----+---/\/\----+------o ---> 0 to 10mA load
. | |
. R1 R2
. 100 190 all resistors 1%
. | | R1 = 10Rs
. ,-------+ | R2 = 2R1 - Rs
. | | |
. | e e
. | Q1 b --+-- b Q2 Q1 Q2 matched pnp
. | c | c pnp Q3 Q4 matched npn
. | | | | low-voltagehigh-gain
. e +-----' |
. b --- | ----------+
. c Q5 +-----, |
. | mps | | |
. | A92 c Q3 | c Q4
. | b --+-- b npn
. | e e
. | | |
. | R3 R4 10k 1%
. | |___________|
. | |
. \ Ib/2 | 270k 4.99k
. / Ib '--/\/\---+--/\/\--- gnd
. \ 100k 0.5W |
. | 0.5W 5% \ 4.99k
. | /
. | 4.99k \
. | ,--/\/\---, | 4.99k
. | | __ | +--/\/\---, 0 to +5V
. '---+--|- \ | 4.99k | __ | out, for
. | >--+---/\/\--+--|- \ | 0 to 10mA
. gnd ---|+_/ | >--+----
. gnd ---|+_/

I enjoyed looking this one over and learned from it. But I have a few
questions.

First, since Q5 nominally needs to split away Ib/2 and its beta is on
the order of 1% or so (maybe 1/2%, but you get the idea), the base of
Q5 will have to rob some current from the collector of Q4. That
current cannot then proceed through the Q1/Q2 mirror. And, I'd guess,
this ultimately will account for a noticeable error at the output (no,
I didn't try to work out the exact amount, but I'm guessing it will be
in the area of maybe 1-5% by itself?) That will add to Q1/Q2 and
Q3/Q4 matching errors. Why didn't you choose to make it Darlington to
nearly eliminate that error?

Ib is in the area of about 1mA (a little less, figuring roughly 2.5V
on the bottom side and 5-6V on the pair of mirrors side, leaving most
of the rest of 250V, maybe 242V or so, across it.) Okay. So 900uA or
so. This sets up about 450uA on each side of the mirror paths. You've
chosen 10 ohms for Rs, for a change of 0-100mV over the range of a
0-10mA load. I understand that R1 can also be seen as two parallel
(Rs+R2) resistors, once for each of the two equal currents that
proceed through Q1 and Q5 when there is no load present. But you
decided on 190 ohms for R2. It turns out that 450uA is one part in 20
of 10mA and that this is also roughly the ratio of Rs to (Rs+R2). So
I think I understand this relationship. But what caused you to set
the 200 ohm emitter leg resistor magnitude in the first place? In
other words, suppose I set Rs to 20 ohms, R2 to 380 ohms and R1 to
200? I think the output would still range over the 0-5V desired
output over the same load current range. The only difference is that
the load would see another tenth volt drop at max load. What was your
thinking for the 200 ohm magnitude, itself?

You set R3 and R4 to 10k. They will yield about a 5V drop (4.5V?). Is
the magnitude of this based upon the tiny (26mV/Ie-in-mA) re, large
enough to greatly overwhelm it? Or some other reasoning?

Thanks,
Jon

 

[Electroniker]

I enjoyed looking this one over and learned from it. But I have a few
questions.

First, since Q5 nominally needs to split away Ib/2 and its beta is on
the order of 1% or so (maybe 1/2%, but you get the idea), the base of
Q5 will have to rob some current from the collector of Q4. That
current cannot then proceed through the Q1/Q2 mirror. And, I'd guess,
this ultimately will account for a noticeable error at the output (no,
I didn't try to work out the exact amount, but I'm guessing it will be
in the area of maybe 1-5% by itself?) That will add to Q1/Q2 and
Q3/Q4 matching errors. Why didn't you choose to make it Darlington to
nearly eliminate that error?

Ib is in the area of about 1mA (a little less, figuring roughly 2.5V
on the bottom side and 5-6V on the pair of mirrors side, leaving most
of the rest of 250V, maybe 242V or so, across it.) Okay. So 900uA or
so. This sets up about 450uA on each side of the mirror paths. You've
chosen 10 ohms for Rs, for a change of 0-100mV over the range of a
0-10mA load. I understand that R1 can also be seen as two parallel
(Rs+R2) resistors, once for each of the two equal currents that
proceed through Q1 and Q5 when there is no load present. But you
decided on 190 ohms for R2. It turns out that 450uA is one part in 20
of 10mA and that this is also roughly the ratio of Rs to (Rs+R2). So
I think I understand this relationship. But what caused you to set
the 200 ohm emitter leg resistor magnitude in the first place? In
other words, suppose I set Rs to 20 ohms, R2 to 380 ohms and R1 to
200? I think the output would still range over the 0-5V desired
output over the same load current range. The only difference is that
the load would see another tenth volt drop at max load. What was your
thinking for the 200 ohm magnitude, itself?

You set R3 and R4 to 10k. They will yield about a 5V drop (4.5V?). Is
the magnitude of this based upon the tiny (26mV/Ie-in-mA) re, large
enough to greatly overwhelm it? Or some other reasoning?

Thanks,
Jon

Nice ASCII art. Can the original poster reveal how this was composed?

 

[JeffM]

Nice ASCII art.
Can the original poster reveal how this was composed?
Blakely LaCroix

All that is required is a text editor with a monospaced font.

This make things easier:
http://translate.google.com/translate?u=http://www.tech-chat.de/aacircuit.html+&langpair=de|en
http://groups.google.com/group/sci....ears-*+*-*-*-*-great-job+Andy's-ASCII-Circuit

 

[Jonathan Kirwan]

Nice ASCII art. Can the original poster reveal how this was composed?

I use a short program I wrote. Source is available on my site, but
this link will get you four files:

http://www.infinitefactors.org/misc/ascii_example.zip

They are the ASC.COM and ASC.SYM files (must run in a DOS box) that I
use; plus HV.ASC, which is an LTSpice schematic example of Winfield's
circuit, and HV.TXT, which is the automated output from ASC.COM. This
allows you to use LTSpice (a free simulator, with schematic capture,
program from linear.com) to capture the schematic and save it and then
run ASC.COM on it to generate output that you can direct to a file and
load with notepad, etc.

There is also http://www.tech-chat.de/, which provides an ASCII
schematic editor called AACircuit. That avoids LTSpice and lets you
directly enter schematics using a specialized editor. I prefer being
able to place my schematics into LTSpice, though. Which is why I
wrote that program to convert. What I wrote is not a panacea, though,
and it cannot handle all forms of LTSpice schematics. But it handles
simpler ones.

If you get my zip file from above, here's the output that was
automatically generated from the schematic included there:

: +V250 +V250
: | |
: | |
: | |
: | |
: | \
: | / R1
: \ \ 10
: / R2 /
: \ 100 |
: / |
: | +---------,
: | | |
: | | |
: | | |
: | \ / \
: | / R3 | LOAD
: | \ 190 v 0
: ,-------------+-------------------, / \ /
: | | | |
: | | | |
: | | | |
: | | | |
: | | | |
: | Q1 e>| |<e Q2 gnd
: | 2N3906 |--+----| 2N3906
: | c/| | |\c
: | | | |
: | | | |
: | | | |
: | +----' |
: | | |
: Q6 e>| | |
: MPSA92 |-------------------------------------------+
: c/| | |
: | | |
: | +----, |
: | | | |
: | | | |
: | | | |
: | Q4 c\| | |/c Q3
: | 2N3904 |--+----| 2N3904
: | e<| |>e
: | | |
: | | |
: | | |
: | \ \
: | / R4 / R5
: | \ 5k \ 5k
: | / /
: | | |
: | '-----+-----'
: \ |
: / R7 |
: \ 100k \
: / / R6
: | \ 270k
: | /
: | |
: | |
: | ,---------+--------,
: | | |
: | | \
: | \ / R12
: | / R8 \ 4.99k
: | \ 4.99k /
: | R10 / |
: | ,----/\/\----, | R11 |
: | | 4.99k | | ,----/\/\----, gnd
: | | | | | 4.99k |
: | | | | | |
: | | | | | |
: | | +V | | | |
: | | | | | | +V |
: | | |+ | | | | |
: | | |\ U1 | | | |+ |
: '--+-----|-\ | R9 | | |\ U2 |
: | >---+----/\/\-----+--+-----|-\ |
: ,---|+/ 4.99k | >---+------Vo
: | |/ opamp2 ,---|+/
: gnd |- | |/ opamp2
: | gnd |-
: -V |
: -V

As you can see, it's serviceable for some things.

Jon

 

[Jonathan Kirwan]

http://www.infinitefactors.org/misc/ascii_example.zip

I updated this, so that the schematic looks much closer to Winfield's.
That link above now has the newer, closer version.

The older version is now:
http://www.infinitefactors.org/misc/orig_ascii_example.zip

Jon

 

[Winfield Hill]

I enjoyed looking this one over and learned from it. But I have a few
questions.

I'm glad you enjoyed it, so did I.

First, since Q5 nominally needs to split away Ib/2 and its beta is on
the order of 1% or so (maybe 1/2%, but you get the idea), the base of
Q5 will have to rob some current from the collector of Q4. That
current cannot then proceed through the Q1/Q2 mirror. And, I'd guess,
this ultimately will account for a noticeable error at the output (no,
I didn't try to work out the exact amount, but I'm guessing it will be
in the area of maybe 1-5% by itself?) That will add to Q1/Q2 and
Q3/Q4 matching errors. Why didn't you choose to make it Darlington to
nearly eliminate that error?

Yes, I thought of that, but my ASCII drawing energy was
running low, and the drawing was getting cluttered, so
I rationalized using the datasheet's typical beta = 150
plot (even tho I know that high-voltage transistors do
suffer in this regard), for a hopeful under 1% error.
So yes, anyway, do make Q5 a Darlington if you like.

Ib is in the area of about 1mA (a little less, figuring roughly 2.5V
on the bottom side and 5-6V on the pair of mirrors side, leaving most
of the rest of 250V, maybe 242V or so, across it.) Okay. So 900uA or
so. This sets up about 450uA on each side of the mirror paths. You've
chosen 10 ohms for Rs, for a change of 0-100mV over the range of a
0-10mA load. I understand that R1 can also be seen as two parallel
(Rs+R2) resistors, once for each of the two equal currents that
proceed through Q1 and Q5 when there is no load present. But you
decided on 190 ohms for R2. It turns out that 450uA is one part in 20
of 10mA and that this is also roughly the ratio of Rs to (Rs+R2). So
I think I understand this relationship. But what caused you to set
the 200 ohm emitter leg resistor magnitude in the first place? In
other words, suppose I set Rs to 20 ohms, R2 to 380 ohms and R1 to
200? I think the output would still range over the 0-5V desired
output over the same load current range. The only difference is that
the load would see another tenth volt drop at max load. What was your
thinking for the 200 ohm magnitude, itself?

The OP wanted a low measurement voltage drop, and so I
picked (or he picked?) 100mV as a conmpromise. Then I
aimed for 1/2 mA (getting 450uA, as you calculated) for
the zero-signal bias current, to insure a more than 1MHz
bandwidth. Then I picked 1mA for the full-scale output
signal current, less could reduce accuracy (compare to
the quiescent level) and more could mean too much power
dissipation in Q5, which was dropping nearly 250V (this
was before I added the 100k 0.5W collector resistor).

You set R3 and R4 to 10k. They will yield about a 5V drop (4.5V?).
Is the magnitude of this based upon the tiny (26mV/Ie-in-mA) re,
large enough to greatly overwhelm it? Or some other reasoning?

That's it, in part, but mostly I was worried about the
offset voltages for the pair of "matched" transistors.

As Jim commented, offset voltages and matching are a big
deal in circuits like this (especially if they are not
made with ICs), and in reality the Q1 Q2 mismatch is a
painful problem. Along with 1% resistor errors it means
there'll be an output zero-error voltage to trim away,
and it can also mean that some of the Ib current won't
cancel out, leaving an error that's proportional to the
250V supply, requiring a second trim on the Ib path.

 

[Winfield Hill]

Nice ASCII art. Can the original poster reveal how this was composed?

By hand, in notepad. I've done hundreds of them here on
s.e.d. over the years. It really doesn't take long once
you get used to it. Also, I prefer the tight drawings I
can make by hand, compared to computer-program assistants.

 

[Jonathan Kirwan]

I'm glad you enjoyed it, so did I.

Occasional gems like this make the rest of the panning worthwhile.

Yes, I thought of that, but my ASCII drawing energy was
running low, and the drawing was getting cluttered, so
I rationalized using the datasheet's typical beta = 150
plot (even tho I know that high-voltage transistors do
suffer in this regard), for a hopeful under 1% error.
So yes, anyway, do make Q5 a Darlington if you like.

Thanks. I though it seemed important for that reason.

There is another thought that comes to mind, but perhaps more from my
hobbyist ignorance about these things. The Q5 collector current
varies from 450uA to 1450uA, or so. A span of 1mA, set by Rs/R1 times
the 10mA max load current. This means that Q5's Vce swings around,
now, since instead of nailing the collector to the virtual ground
you've inserted the 100k to share some of the Vce and dissipation.
Wouldn't that mean not only is there an effect due to siphoning off
needed base current from the mirror path, but yet another to the Early
effect, yielding an additional effect due to beta variation? With
this kind of Vce variation, not so far from the VA of the device, my
memory nags at me that the beta does vary enough to think about here.

The OP wanted a low measurement voltage drop, and so I
picked (or he picked?) 100mV as a conmpromise. Then I
aimed for 1/2 mA (getting 450uA, as you calculated) for
the zero-signal bias current, to insure a more than 1MHz
bandwidth. Then I picked 1mA for the full-scale output
signal current, less could reduce accuracy (compare to
the quiescent level) and more could mean too much power
dissipation in Q5, which was dropping nearly 250V (this
was before I added the 100k 0.5W collector resistor).

I noted the 100k collector resistor and gathered that purpose. With
the collector moving around like that because of the 100k, though,
doesn't it then impact the frequency response? For frequency response
reasons, wouldn't it be better to just nail the collector down?

That's it, in part, but mostly I was worried about the
offset voltages for the pair of "matched" transistors.

Ah. I missed that detail. I think I see what you mean. I'll look
more closely.

As Jim commented, offset voltages and matching are a big
deal in circuits like this (especially if they are not
made with ICs), and in reality the Q1 Q2 mismatch is a
painful problem. Along with 1% resistor errors it means
there'll be an output zero-error voltage to trim away,
and it can also mean that some of the Ib current won't
cancel out, leaving an error that's proportional to the
250V supply, requiring a second trim on the Ib path.

I see those two points, well. Thanks.

Jon

 

[Winfield]

There is another thought that comes to mind, but perhaps more from my
hobbyist ignorance about these things. The Q5 collector current
varies from 450uA to 1450uA, or so. A span of 1mA, set by Rs/R1 times
the 10mA max load current. This means that Q5's Vce swings around,
now, since instead of nailing the collector to the virtual ground
you've inserted the 100k to share some of the Vce and dissipation.
Wouldn't that mean not only is there an effect due to siphoning off
needed base current from the mirror path, but yet another to the Early
effect, yielding an additional effect due to beta variation? With
this kind of Vce variation, not so far from the VA of the device, my
memory nags at me that the beta does vary enough to think about here.

No serious effect from V_A -- that changes Vbe a little bit,
yes, but it's inside a feedback loop and simply changes the
voltage on Q4's collector a little bit.

I noted the 100k collector resistor and gathered that purpose. With
the collector moving around like that because of the 100k, though,
doesn't it then impact the frequency response? For frequency response
reasons, wouldn't it be better to just nail the collector down?

That's a good point, even though Ccb for a mpsA92 is only
about 1.2pF (for Vce above 25V) the G=1000 ac stage gain!
will cause mucho trouble. For my spice tests I added 100pF
in parallel with the 100k, speeding up the response to 5MHz
(compared to 80kHz without the cap) and 40ns rise/falltime.

 

[Jonathan Kirwan]

No serious effect from V_A -- that changes Vbe a little bit,
yes, but it's inside a feedback loop and simply changes the
voltage on Q4's collector a little bit.

I was thinking not in those terms, though it did cross my mind and I
tossed it out for the same reasons you just mentioned. It was just
that I imagined about impact on beta, not Vbe. Now that I think more
on what I remember, (1+Vce/VA)*beta (though that could be a completely
faulty lark of memory), even that wouldn't be all that important. The
beta would be at least as good, and get better, not worse. So never
mind. In short, I've dropped it out of any thoughts.

That's a good point, even though Ccb for a mpsA92 is only
about 1.2pF (for Vce above 25V) the G=1000 ac stage gain!
will cause mucho trouble. For my spice tests I added 100pF
in parallel with the 100k, speeding up the response to 5MHz
(compared to 80kHz without the cap) and 40ns rise/falltime.

A speed-up cap. I should have figured on my own. Thanks.

Jon