horrible development

[dmm]

OK, we have a BIST (built-in self-test) bus that can have sine waves
from a couple volts to about 100 volts p-p. So I did this into an
analog mux:

________
| |
| |
| |
bus--->------+-------r1-----+------| mux |-->--opamp-->--adc
| | | hc4051 |
| r2 | |
| | | |
| gnd | |---- +5
| | |
| | |---- -5
+-------r3-----+------| |
| | |----gnd
r4 | |
| | |
gnd ________


where one divider is about 4:1, for low level signals, and the other
is about 21:1 for the big stuff. ADC range is +-3.5, and I can take a
lot of samples and average to get dc, and simultaneously average the
abs value to get ac.

What happens is that when I have a big signal, selecting the
high-ratio divider, the output of the 4:1 divider blows through the
esd diodes of the mux and sneaks its way into the output, so I get a
lot more signal than the 21:1 attenuated level I want, and it's of
course distorted as well.

Bummer. One of the HC designers once assured me this wouldn't happen,
but that was another vendor (Moto) and the parts we have here are
Fairchild so I guess different processes can do this.

Bummer.

So, I can kluge on a couple of 1N5711's as clamps, really ugly, or
find another drop-in part that doesn't blow through.

Any suggestions?


John

I haven't looked at all the posts with regards to this problem, so please
forgive me if I'm reposting someone else's answer.

Since the bus is common to both inputs, except with the attenuation,
you will be getting 25volts at the 4:1 input when the bus is at 100volts.
This vastly exceeds the maximum input voltage of this device when you're
only supplying it with +/- 5V DC.

Increase the attenuation of the 4:1 input to 10:1, and you shouldn't have
any more problems.

No wonder you're damaging the input protection diodes and getting
unwanted feedthrough. Got nothing to do with the chip manufacturing
processes.


regards
David

 

[John Larkin]

I would rule that out from the start, clipping diodes, as the distortion
generated may make its way back to the driving source.
Just use some sort of (semiconductor) switch to short that input in not selected.

The 4:1 voltage divider is 100k to 33.2k, into the mux of the BIST
(built-in self-test) ADC. Each of the eight 50-ohm DDS outputs (which
can be as high as 100 volts p-p) can be relay-switched from the user
connector to a test bus, and it's this bus that drives the two
dividers into the mux. There's also a frequency counter hooked to the
test bus, and some other mux inputs to the adc. So a tiny amount of
distortion wouldn't matter.

The BIST allows the user to poke a macro command into a VME register
and have the module pretty much test itself... takes about 10 seconds.
This is a functional test, not really an accuracy test, so the failure
limits are pretty broad, 0.1% on frequency and 3% on amplitude. Each
channel also has six SSRs and a switchable isolation transformer in
its output, and BIST tests all of that, too. The code was an immense
pita. I'm still clocking the SPI adc one time more than the datasheet
says I should, and I guess I'll never know why.

Maybe I'll just use a DG508 next rev, powered by +-12.

John

 

[John Larkin]

I haven't looked at all the posts with regards to this problem, so please
forgive me if I'm reposting someone else's answer.

Since the bus is common to both inputs, except with the attenuation,
you will be getting 25volts at the 4:1 input when the bus is at 100volts.
This vastly exceeds the maximum input voltage of this device when you're
only supplying it with +/- 5V DC.

Increase the attenuation of the 4:1 input to 10:1, and you shouldn't have
any more problems.

Of course I could use a single high-ratio attenuator, 20:1 actually,
but then I'd be throwing away low-end resolution. I considered that
option, but then I'd have to change the code, and open up my test
limits.

No wonder you're damaging the input protection diodes and getting
unwanted feedthrough. Got nothing to do with the chip manufacturing
processes.

There's less than 500 uA going into the esd diodes, and nothing is
being damaged; I'm just getting a gain error. Hell, if I were a real
hack, I could just change my test limits.

As Jim figured out, the 0.6 volt swing past the rails is likely
turning on one of the cmos pass transistors and dumping that current
into the analog output node. I'm glad I understand that now.

They could have designed the chip so that this doesn't happen.

John

 

[Jim Thompson]

Of course I could use a single high-ratio attenuator, 20:1 actually,
but then I'd be throwing away low-end resolution. I considered that
option, but then I'd have to change the code, and open up my test
limits.



There's less than 500 uA going into the esd diodes, and nothing is
being damaged; I'm just getting a gain error. Hell, if I were a real
hack, I could just change my test limits.

As Jim figured out, the 0.6 volt swing past the rails is likely
turning on one of the cmos pass transistors and dumping that current
into the analog output node. I'm glad I understand that now.

They could have designed the chip so that this doesn't happen.

John

Not easily. The MUX is specified as bi-directional.

...Jim Thompson

 

[krw]

I've been known to put a note in the database, "NO Motorola" ;-)

We had to do that a few moons ago. The TI Moto unit caused a few
multi-million dollar mainframes to catch fire (secondary breakdown
causing contactors to remain closed) in the customers' office.
Management wasn't impressed. I proved the Siggy devices bullet
proof, TI good enough, and Moto pure crap.

 

[Terry Given]

We had to do that a few moons ago. The TI Moto unit caused a few
multi-million dollar mainframes to catch fire (secondary breakdown
causing contactors to remain closed) in the customers' office.
Management wasn't impressed. I proved the Siggy devices bullet
proof, TI good enough, and Moto pure crap.

In what way? I'm extremely curious to her boht Keith and Jims comments
in this regard

Cheers
Terry

 

[Fred Bartoli]

Terry Given a écrit :

In what way? I'm extremely curious to her boht Keith and Jims comments
in this regard

Plus me think that such pending disaster depending on a component fail
isn't very brilliant design.

 

[Lionel]

Terry Given a écrit :

Plus me think that such pending disaster depending on a component fail
isn't very brilliant design.

Indeed. Doesn't anyone practice 'worst-case' design any more?

 

[John Larkin]

On Sun, 25 Feb 2007 16:00:32 -0800, John Larkin


Well, Rob was harassing me about the inelegance of my dual-schottky
kluge, so we came up with this:

+3.3V
|
|
6.8v k ________
zener a | |
| | |
| | |
bus--->------+-------r1-----+------| mux |-->--opamp-->--adc
| | | hc4051 |
| r2 | |
| | | |
| gnd | |---- +5
| | |
| | |---- -5
+-------r3-----+------| |
| | |----gnd
r4 | |
| | |
gnd ________

which clamps the swing to about +3.9 and -3.5, fine for the +-3.3
range of the adc and fine for the +-5 range of the mux.

Don't you just hate it when underlings are right?

John

 

[Jim Thompson]

On Wed, 28 Feb 2007 23:02:15 +0100, Fred Bartoli
[snip]

Plus me think that such pending disaster depending on a component fail
isn't very brilliant design.

Indeed. Doesn't anyone practice 'worst-case' design any more?

I certainly do. One of these days perhaps one of my clients will come
forward and tell what grilling I put them through before I agree to a
specification. Just grilled one today ;-)

...Jim Thompson

 

[krw]

In what way?

They were susceptible to secondary breakdown at far lower voltages
than they avalanched. I couldn't get a Siggy part to go into
secondary breakdown. I could get some TI parts to fail in SB but
the energy needed was way outside what we abusing the parts with.
;-)

I'm extremely curious to her boht Keith and Jims comments
in this regard

A little bit of failure analysis showed the difference between the
parts. The Moto part was basically an IC part with a huge
transistor glued on. The Siggy part was basically a large power
transistor with a bit of logic glued to the front. Since it was a
power device...

 

[Terry Given]

On Sun, 25 Feb 2007 16:00:32 -0800, John Larkin


Well, Rob was harassing me about the inelegance of my dual-schottky
kluge, so we came up with this:






which clamps the swing to about +3.9 and -3.5, fine for the +-3.3
range of the adc and fine for the +-5 range of the mux.

Don't you just hate it when underlings are right?

John

Excellent. Buy that man a beer!

Cheers
Terry

 

[krw]

Terry Given a écrit :

Plus me think that such pending disaster depending on a component fail
isn't very brilliant design.

When you turn of the power switch and it comes back on by itself,
bad things happen (since the unit thinks it's off). Even
mechanical switches fail closed.

 

[John Larkin]

Indeed. Doesn't anyone practice 'worst-case' design any more?

True worst-case design, adding all the possible tolerances in one
direction, is sometimes unreasonable, as the probability of a really
nasty stackup is below the MTBF for other reasons. RMS addition is
more realistic.

Sometimes you get performance by pushing the parts. We sometimes have
a product that's almost all worst-case designed, but has one or two
performance-critical parts that are using typical, often beyond-specs,
part behavior to get serious, sellable advantages. Like using a 2.5
volt reverse rated microwave schottky diode at 6 volts. It's a
calculated risk.

Do this too much, and you get into trouble.

Some parts simply don't spec the thing that matters, like oscillator
phase noise maybe. So you test a lot of different parts and pick the
best one.

John

 

[Terry Given]

They were susceptible to secondary breakdown at far lower voltages
than they avalanched. I couldn't get a Siggy part to go into
secondary breakdown. I could get some TI parts to fail in SB but
the energy needed was way outside what we abusing the parts with.
;-)




A little bit of failure analysis showed the difference between the
parts. The Moto part was basically an IC part with a huge
transistor glued on. The Siggy part was basically a large power
transistor with a bit of logic glued to the front. Since it was a
power device...

Thanks mate

Cheers
Terry

 

[Jeroen Belleman]

]
which clamps the swing to about +3.9 and -3.5, fine for the +-3.3
range of the adc and fine for the +-5 range of the mux.

Don't you just hate it when underlings are right?

Qui craint des collaborateurs éminents, n'est pas un chef.

Jeroen Belleman

 

[dmm]

Of course I could use a single high-ratio attenuator, 20:1 actually,
but then I'd be throwing away low-end resolution. I considered that
option, but then I'd have to change the code, and open up my test
limits.



There's less than 500 uA going into the esd diodes, and nothing is
being damaged; I'm just getting a gain error. Hell, if I were a real
hack, I could just change my test limits.

As Jim figured out, the 0.6 volt swing past the rails is likely
turning on one of the cmos pass transistors and dumping that current
into the analog output node. I'm glad I understand that now.

They could have designed the chip so that this doesn't happen.

John

Perhaps using a different device would be a more optimal solution,
particularly for the higher voltages experienced.

Where I worked previously, we designed an automatic test jig that
utilised NAIS AQW212A PhotoMOS devices, and they worked very well.
That series had devices that worked up to 600V @ 40mA load current.
The last price I obtained from Mouser (early 2006) was roughly US$2 each
for the '212A's.

Regards
David

 

[Phil Hobbs]

On Sun, 25 Feb 2007 16:00:32 -0800, John Larkin


Well, Rob was harassing me about the inelegance of my dual-schottky
kluge, so we came up with this:




which clamps the swing to about +3.9 and -3.5, fine for the +-3.3
range of the adc and fine for the +-5 range of the mux.

Don't you just hate it when underlings are right?

John

Hmm, possibly quite nice, but didn't you mention wanting to go to higher
frequency BIST eventually? What's the capacitance of that zener?
1N5711s I know about. Maybe a BE junction of some reasonable transistor
would have lower capacitance and a comparable voltage drop. (Of course
that heads back into datasheet *terra incognita*.)

Cheers,

Phil Hobbs

 

[John Larkin]

]
which clamps the swing to about +3.9 and -3.5, fine for the +-3.3
range of the adc and fine for the +-5 range of the mux.

Don't you just hate it when underlings are right?

Qui craint des collaborateurs éminents, n'est pas un chef.

That was a bit much for my rusty high school French, but Babelfish
gives

"Who fears eminent collaborators, is not a chief."

which looks pretty good for a computer translation. Unless, of course,
they cheated by including common sayings.

But yes, it takes guts to brainstorm.

John

 

[John Larkin]

Hmm, possibly quite nice, but didn't you mention wanting to go to higher
frequency BIST eventually?

Yup. We're planning versions of this module up to 25 MHz at least. The
crystal clock is 32 MHz and the fpga can clock multiply... we're
currently plunking along at 64 MHz internally, which should make
decent 16 MHz sinewaves. The dacs are good for 140 MHz, and the analog
stuff downstream of the dacs is plenty fast.

What's the capacitance of that zener?

My trusty AADE meter reports 53 pF at zero bias, so it should be a
bunch less as used here. This is a regular 1N751-series type.

I wonder if anybody makes really tiny geometry zeners.

But one of the mux inputs is the output of an AD8361 integrated RF
detector, currently unstuffed. We figure that if we do a serious hf
version, we'll use that as the amplitude detector at the higher
frequencies. The dinky ADS7866 serial adc wouldn't give us useful
samples above about a hundred khz anyhow.

1N5711s I know about. Maybe a BE junction of some reasonable transistor
would have lower capacitance and a comparable voltage drop. (Of course
that heads back into datasheet *terra incognita*.)

A b-e junction could be a very low-c zener, but they tend to run
closer to 5 volts.

The BIST philosophy is to detect most reasonable field failure modes,
knowing that a serious production test was once done. So I'm checking
amplitudes at 10 KHz (software rectifying the samples), checking
frequency (separate xo as ref, counter in the fpga), and verifying all
the SSR transformer switching paths and such.

I could post the BIST schematic is anyone is interested. I posted a
pic of the board to abse a few weeks ago.

I wish more people would post the stuff they're actually designing,
instead of asking cryptic questions.

John