horrible development

[Jim Thompson]

On Mon, 26 Feb 2007 08:03:19 -0700, Jim Thompson
[snip]

Ooops! Strike that second suggestion :-(

...Jim Thompson

Dang, you beat me to it.

But you can do a tapped divider and use the mux to ground taps on a
series-string divider, sort of like what you suggest.

But why do these chips do this? How does the esd diode current find
its way into the output? Incidentally, the effect is almost perfectly
symmetric for high and low clmping.

John

GND is the substrate (NMOS bodies _are_ the substrate).

VDD has all the PMOS bodies tied to it.

There is nothing there to keep currents from going all over hell and
back when ESD is forward-biased.

...Jim Thompson

 

[Joerg]

On Mon, 26 Feb 2007 07:19:19 -0800, John Larkin

[snip]

The spec sheet names a maximum esd diode clamp current. It doesn't
mention that the chip becomes non-functional at about 1% of that
current.

Maybe because the marketeers decided that such mention wouldn't look good.

I could be pompous and remind everyone how many times I've said DON'T
DO IT ;-)

But it's soooo tempting....

 

[Jim Thompson]

I think it is in spec, or at least that the spec is woefully
misleading. It's screwing up at about 1% of the epecified esd clamp
current.

John

Sno-o-o-ort!

I just realized it's not the ESD that's causing your fault.

Hand-holding available upon request ;-)

...Jim Thompson

 

[John Larkin]

Sno-o-o-ort!

I just realized it's not the ESD that's causing your fault.

Hand-holding available upon request ;-)

...Jim Thompson

So maybe it's driving the source enough to turn on the series fet? At
0.6 volts gate threshold? I guess that's possible.

It does make sense from the behavior I'm seeing. I wonder if an old
CD4051 would have higher thresholds, and work?

There are some parts that don't do this, and in fact let unselected
inputs go far beyond the rails. But none are 4051 pinout, I think.

We were in the midst of a pretty serious crisis when we designed this
board (we had to completely redesign the fpga and firmware for a
screwed-up digital delay generator) and we knew we hadn't spent enough
time checking and reviewing. The fact that we can ship the first rev,
with one wire and two diodes, ain't too shabby.

John

 

[Jim Thompson]

So maybe it's driving the source enough to turn on the series fet? At
0.6 volts gate threshold? I guess that's possible.

Yep. For 74HC... it's _likely_.

It does make sense from the behavior I'm seeing. I wonder if an old
CD4051 would have higher thresholds, and work?

I don't have enough familiarity with the CD stuff to know, but I'm
sure the threshold is higher. I don't know what the ESD structure is
like though in these devices.

There are some parts that don't do this, and in fact let unselected
inputs go far beyond the rails. But none are 4051 pinout, I think.

We were in the midst of a pretty serious crisis when we designed this
board (we had to completely redesign the fpga and firmware for a
screwed-up digital delay generator) and we knew we hadn't spent enough
time checking and reviewing. The fact that we can ship the first rev,
with one wire and two diodes, ain't too shabby.

John

If you're only doing two channels, my 74HC4052 suggestion should work.

...Jim Thompson

 

[John Larkin]

Yep. For 74HC... it's _likely_.


I don't have enough familiarity with the CD stuff to know, but I'm
sure the threshold is higher. I don't know what the ESD structure is
like though in these devices.

Think "latchup." The old A series would go up in flames from the
tiniest noise spike.

If you're only doing two channels, my 74HC4052 suggestion should work.

Actually, I've got a bunch of other stuff mux'd in: an LM45
temperature sensor, another bus voltage to monitor, a cute little
AD8361 rf detector (for the eventual 20 MHz version of the board) and
an adc ground/autozero thing.

So I guess I'll stick with the schottkies.

John

 

[Terry Given]

On Mon, 26 Feb 2007 07:19:19 -0800, John Larkin

[snip]

The spec sheet names a maximum esd diode clamp current. It doesn't
mention that the chip becomes non-functional at about 1% of that
current.

Maybe because the marketeers decided that such mention wouldn't look good.

I could be pompous and remind everyone how many times I've said DON'T
DO IT ;-)

But it's soooo tempting....

You guys'll love this story.

Working at a large asian videoscreen company on some EMI issues, I was
asked to look at a comms problem late in the afternoon. an I2C
connection had mysteriously stopped working. The actual circuit uses a
HC4053 to switch the external I2C between a couple of different things.
And it was refusing ot output a logic zero, which upset the downstream
logic.

A bit of probing with a scope showed the 3.3V chip have 4V outputs.
Luckily the schematic used useful supply names like Vcc1 and Vcc2, and
also used "hidden" supply connections, making it almost impossible to
figure out what chip had what supply voltage. So I did it with a DMM on
beep.

Turns out the dangly wires are 5V, but all the innards are 3V3. And of
course there was no thought put into voltage level translation (note:
they have sold hundreds of millions of dollars of these things).

At the engineering management meeting the next morning, the chief
engineer gave his report, which basically said faulty 4053 chips were
the root cause. And his solution was:

- desolder faulty chip
- cut trace under IC
- re-solder faulty chip (IM NOT KIDDING)
- add dangly wires
- tack an OR gate on top of another chip
- use the OR gate to "buffer" the non-zero signal, to get a nice clean zero.

The owner of the company asked for my thoughts, at which point I gave a
short lecture on whats inside ICs, what can happen when current is
bunged thru the protection diodes (summary: anything, but always bad),
and how the circuit was designed to force it to happen.

At lunch later that day, I was asked where I got my doctorate. They were
astounded to discover I didnt have one, and that I didnt even bother
finishing my ME thesis (somebody offerred to triple my pay, so I
emigrated instead).

I ended up doing a detailed review of how often this occurred within the
design. The answer? hundreds of times. One high-speed data chip had
about 35 such connections; the resultant DC power was significant,
although the IC at least didnt flip out.

Although the funniest was the FPGA, which had separate Vccio pins that
could have been tied to 5V, but werent!

the relevant IIC 5V output had a series resistor anyway, so the kludge
involved increasing it a bit, and tacking on a shunt resistor.


and the moral of the story is:

NEVER hide the power supply connections on a schematic, and ALWAYS use
sensible names for power supplies, like +5V_iso

which at least gives a peer-reviewer a chance.


Cheers
Terry

 

[Lionel]

The spec sheet names a maximum esd diode clamp current. It doesn't
mention that the chip becomes non-functional at about 1% of that
current.

Surely it's common sense not to put signals through ESD protection
diodes in the first place? And even if it works with one brand of
chips, what happens if Purchasing switches to another supplier?

 

[Ian]

"Fred Bartoli"

John Larkin a écrit :

There are some switches designed to handle fault over voltage up to (from
memory) 44V.
I think they are marketed for automotive environments and ISTR that there
are some cloned on the 405x family.
The keyword is fault tolerant I think.

Don't have much time to search, but maxim comes to mind and probably moto,
oops onsemi.

If you go clamping and with a new rev. then I'd drop the leaky schottkies,
go with a BAV99, split the divider's top resistance and clamp there.

"Fault protected" is the ADI term, see ADG438 for example.

Regards
Ian

 

[John Larkin]

If you go clamping and with a new rev. then I'd drop the leaky
schottkies, go with a BAV99, split the divider's top resistance and
clamp there.

That's elegant. I'll do that.

John

 

[John Larkin]

Surely it's common sense not to put signals through ESD protection
diodes in the first place? And even if it works with one brand of
chips, what happens if Purchasing switches to another supplier?

If I specify brand X, they buy brand X.

John

 

[Eeyore]

If I specify brand X, they buy brand X.

Being the Boss is handy like that !

Graham

 

[John Larkin]

Being the Boss is handy like that !

Graham

We just put a note in the part database record "FAIRCHILD ONLY" or
some such. We may have stock number XXXX that has multiple vendors
specified as acceptable, and essentially the same part under a
different stock number YYYY that is restricted to one vendor, or with
some other qualifier.

John

 

[Eeyore]

We just put a note in the part database record "FAIRCHILD ONLY" or
some such. We may have stock number XXXX that has multiple vendors
specified as acceptable, and essentially the same part under a
different stock number YYYY that is restricted to one vendor, or with
some other qualifier.

I was teasing slightly !

Having spent some time as a 'components engineer' I fully understand the
importance of proper purchasing specs.

Graham

 

[Jim Thompson]

We just put a note in the part database record "FAIRCHILD ONLY" or
some such. We may have stock number XXXX that has multiple vendors
specified as acceptable, and essentially the same part under a
different stock number YYYY that is restricted to one vendor, or with
some other qualifier.

John

I've been known to put a note in the database, "NO Motorola" ;-)

...Jim Thompson

 

[Richard Henry]

OK, we have a BIST (built-in self-test) bus that can have sine waves
from a couple volts to about 100 volts p-p. So I did this into an
analog mux:

________
| |
| |
| |
bus--->------+-------r1-----+------| mux |-->--opamp-->--adc
| | | hc4051 |
| r2 | |
| | | |
| gnd | |---- +5
| | |
| | |---- -5
+-------r3-----+------| |
| | |----gnd
r4 | |
| | |
gnd ________

where one divider is about 4:1, for low level signals, and the other
is about 21:1 for the big stuff. ADC range is +-3.5, and I can take a
lot of samples and average to get dc, and simultaneously average the
abs value to get ac.

What happens is that when I have a big signal, selecting the
high-ratio divider, the output of the 4:1 divider blows through the
esd diodes of the mux and sneaks its way into the output, so I get a
lot more signal than the 21:1 attenuated level I want, and it's of
course distorted as well.

Bummer. One of the HC designers once assured me this wouldn't happen,
but that was another vendor (Moto) and the parts we have here are
Fairchild so I guess different processes can do this.

Poor dumb little me. I would have complied with the Fairchild
"absolute maximum" spec for the inputs (0.5 volts beyond the rails).
I guess that's what comes from thinking inside the box.

 

[martin griffith]

OK, we have a BIST (built-in self-test) bus that can have sine waves
from a couple volts to about 100 volts p-p. So I did this into an
analog mux:

________
| |
| |
| |
bus--->------+-------r1-----+------| mux |-->--opamp-->--adc
| | | hc4051 |
| r2 | |
| | | |
| gnd | |---- +5
| | |
| | |---- -5
+-------r3-----+------| |
| | |----gnd
r4 | |
| | |
gnd ________


where one divider is about 4:1, for low level signals, and the other
is about 21:1 for the big stuff. ADC range is +-3.5, and I can take a
lot of samples and average to get dc, and simultaneously average the
abs value to get ac.

What happens is that when I have a big signal, selecting the
high-ratio divider, the output of the 4:1 divider blows through the
esd diodes of the mux and sneaks its way into the output, so I get a
lot more signal than the 21:1 attenuated level I want, and it's of
course distorted as well.

Bummer. One of the HC designers once assured me this wouldn't happen,
but that was another vendor (Moto) and the parts we have here are
Fairchild so I guess different processes can do this.

Bummer.

So, I can kluge on a couple of 1N5711's as clamps, really ugly, or
find another drop-in part that doesn't blow through.

Any suggestions?


John

Could you just do a virtual earth with the opamp, and scale the input
resistors? Use the parallel diodes on the inputs of the mux to limit
the volts when the switch is disconnected


martin

 

[John Larkin]

Poor dumb little me. I would have complied with the Fairchild
"absolute maximum" spec for the inputs (0.5 volts beyond the rails).
I guess that's what comes from thinking inside the box.

Well, like I said, we knew we were rushing this design. An 8-channel
DDS synthesizer VME module, with a 68K CPU and two fpga's, one a BGA,
works on first etch with one jumper and two diodes. So shoot me.

John

 

[Jan Panteltje]

Poor dumb little me. I would have complied with the Fairchild
"absolute maximum" spec for the inputs (0.5 volts beyond the rails).
I guess that's what comes from thinking inside the box.

I would rule that out from the start, clipping diodes, as the distortion
generated may make its way back to the driving source.
Just use some sort of (semiconductor) switch to short that input in not selected.

 

[Spehro Pefhany]

I would rule that out from the start, clipping diodes, as the distortion
generated may make its way back to the driving source.
Just use some sort of (semiconductor) switch to short that input in not selected.

Maybe one of those little single-gate bilateral switches. Hard to hack
in as a fix, but I've done it with AWG39 magnet wire and epoxy.


Best regards,
Spehro Pefhany