Frequency Divider

[Virium]

Hello everybody, asking for some help with a frequency divider using a D flip flop.
The chip on the left is a D flip flop, I feed a signal (f) in to the clock and it outputs it to me halved (f2), it works fine.
I am trying to simulate the same using logic gates, and getting no results.
The output is nothing I desire, the pulses are about 25x faster and the clock signal turns into DC.
What am I doing wrong here ?
Thank you for your time

 

[(*steve*)]

the problem is that your gate version passes D to Q while the clock is high. The other one does it as the clock goes high.

the practice upshot is that your gate version is not limited to a single transition during each clock cycle

 

[Harald Kapp]

To avoid this, look up master-slave flip flop.