Experiment Platform for the MC68000

[Quiki]

For fun, I am resurrecting an old MC68000P on a breadboard. I've never designed a computer system from scratch before, so to start I hooked the 68000's address and control lines to some I/O from a PC-104 card on a 200MHz Linux computer. The program initializes the I/O pins, and then runs through a state machine to properly communicate with the chip. First the processor's /HLT and /RST lines are asserted for 1/2 a second to reset, then released. Next the card waits for the 68000 to assert its /AS. Upon seeing that, the card sends a /DTACK. And then it releases /DTACK once /AS is negated. The data bus is hard wired with pull-up/down resistors for a 'branch-back-to-itself' instruction. Now the problem...

I can start the processor and, after a few clock cycles, the processor does 2 16-bit read cycle to fetch the SP. Next it should read 2 more for the PC. But instead it hangs without ever asserting /AS again to start the next bus cycle. I made a number of minor timing changes, with no improvment. Also I notice that the behavior is not always consistent, with a bus cycle starting without the Data Strobes being asserted. (Maybe timing irregularities from the Linux board?)

I read in the documentation that there is a minimum clock frequency for the chip (that I am certainly violating) and that the clock signal must be square (which I am crudely approximately). Do clock irregularities really matter in a static processor?? If I run off a 1MHz crystal clock, the processor makes all 4 reads.

Any other ideas? Thanks a lot!

 

[Quiki]

So an update... For more fun, I hooked the 68k up to an FPGA instead of the PC-104 to eliminate the very crude signal timing performance. After doing that, 68k worked fine, even down to a couple Hz. I suppose the processor may be sensitive to irregularities in clock duty cycle.

BTW, after verifying the logic in the FPGA (avoiding tedious wiring of discrete chips), I finally broke down an wired up a version all in discrete logic, with 27256 EEPROM, 6264 SRAM, etc. This FPGA is still in there, but now as a 'chip selected' device for sound, VGA display, PC keyboard input, etc.

68k forever, right??

 

[(*steve*)]

The CPU may be sensitive to slow rise and fall times on the clock, and certainly glitches on the clock are to be avoided.