on the nov 29 post some of you have noticed the above rigol screen image has only one fire pulse , blue , not two. there is suppose to be a blue
fire pulse after every -71 deg input pulse.
oh , every other pulse , as shown ,could work. some of the time. in a 4-cycle engine
this post is to bring you up to date. the code was edited. there are new lines ... 39 - 55 and 66. a new user variable is d3 ,line 12.
what is going on is as soon as we have the TMR0 value it goes both to nmbr then to d3. and the plan is to delay an amount in d3
after the line 33 lead edge of a -71 deg pulse is detected. with the idea being the fire delay will be identical at least for 2 -71 pulses.
now the code looked good when i stopped the editing. the next step was to wire the uC into a breadboard and apply an input pulse.
and monitor this pulse and the fire pulse too. and see if there is now a fire pulse after every -71 pulse and if the delay between them
is the same for 2 pairs of these two pulses.
good news there is a fire pulse for every 71 pulse.
bad news , the delay between them is unequal . this you can see on the rigol screen image
here is the screen image and scans of the 3 pages of assembly code
fire pulse after every -71 deg input pulse.
oh , every other pulse , as shown ,could work. some of the time. in a 4-cycle engine
this post is to bring you up to date. the code was edited. there are new lines ... 39 - 55 and 66. a new user variable is d3 ,line 12.
what is going on is as soon as we have the TMR0 value it goes both to nmbr then to d3. and the plan is to delay an amount in d3
after the line 33 lead edge of a -71 deg pulse is detected. with the idea being the fire delay will be identical at least for 2 -71 pulses.
now the code looked good when i stopped the editing. the next step was to wire the uC into a breadboard and apply an input pulse.
and monitor this pulse and the fire pulse too. and see if there is now a fire pulse after every -71 pulse and if the delay between them
is the same for 2 pairs of these two pulses.
good news there is a fire pulse for every 71 pulse.
bad news , the delay between them is unequal . this you can see on the rigol screen image
here is the screen image and scans of the 3 pages of assembly code

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