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Cuk converter bizzare control loop

  • Thread starter robert lafrance
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K

Ken Smith


Go back and look at the drawing above again and lets see if I can find
where you don't follow the logic.

Do you agree that the PWM chip turns the transistor off somewhere in the
T1 part of my drawing?

Do you agree that the added energy put into the inductors is transfered
to the output over the time T2?

Is the centroid of T1 at the same time as the centroid of T2?

Is information from time T1 determining what happens at time T2?

Is there any attenuation with increased frequency in this?

Is the delay from T1 to T2 a constant time and therefor increasing
linearly with frequency?


You must bear in mind that current in L2 is 'output' current, the inductor
is connected to the output. Current (Energy) is flowing in the inductor, and
the output, during 'both' T1 AND T2.

Yes but some energy flow during T2. All the information the switcher chip
used was in T1. The information came from T1 and the result happened in
T2. That is a transport delay when T2 is later than T1.

Your description of the CUK sounds more like you are thinking about a SEPIC.

No, we talking about a Cuk converter here.
 
G

Genome

Ken Smith said:
Go back and look at the drawing above again and lets see if I can find
where you don't follow the logic.

Do you agree that the PWM chip turns the transistor off somewhere in the
T1 part of my drawing?

Nope, it turns it off at the end of T1.
Do you agree that the added energy put into the inductors is transfered
to the output over the time T2?

Nope, The energy in L2 is completely delivered to the output during T2 if
you are operating it discontinuously.

Is the centroid of T1 at the same time as the centroid of T2?

T1 ends, T2 begins. What is the centroid?

I'll warn you,

You'd better be good here. I'm not Gods gift to maths but take care.

Now you're analysing a CUK converter with discontinuous inductor current.

Either do the job right or shut the **** up.

([email protected] forging knowledge)


Is information from time T1 determining what happens at time T2?

It Does.
Is there any attenuation with increased frequency in this?

No, for discontinuous operation the result is zero order.
Is the delay from T1 to T2 a constant time and therefor increasing
linearly with frequency?

When T1 ends T2 begins. I see no delay.
Yes but some energy flow during T2. All the information the switcher chip
used was in T1. The information came from T1 and the result happened in
T2. That is a transport delay when T2 is later than T1.

DNA
 
K

Ken Smith

Ken Smith said:
Nope, it turns it off at the end of T1.
Newsgroups: sci.electronics.design
Subject: Re: Cuk converter bizzare control loop
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Here's my drawing back for refence with some added labels


(A) marks where the transistor turns on. The current starts to build up
in L2 from zero.

(B) marks the point where the transistor turns off in the undisturbed
case.

(C) marks the point where the transistor turns off in the disturbed state.

The line (B)-(D) is the falling current in the undisturbed state. (D) is
where it hits zero.

The line (C)-(E) is the falling current in the disturbed state. (E) is
where it hits zero.

Nope, The energy in L2 is completely delivered to the output during T2 if
you are operating it discontinuously.

The extra energy that is put into L2 during the time (B)-(C) is delivered
to the output during T2. Do you see that now?


[...]
When T1 ends T2 begins. I see no delay.

Do go back and look at the drawing. T1 and T2 overlap.


T1 *********
T2 *****************************

They overlap like this:

Do you understand that part now?


Now consider when it is that the switcher chip decided to turn off the
transistor. All of the information it use must have come from before the
end of the time T1. Do you understand that?


Consider when the results of the switcher chips switching are seen in the
output side. It is not until the end of T2 that all of the extra energy
has been delivered. Do you understand that?

Do you now see the delay?
 
G

Genome

Ken Smith said:
Here's my drawing back for refence with some added labels



(A) marks where the transistor turns on. The current starts to build up
in L2 from zero.

(B) marks the point where the transistor turns off in the undisturbed
case.

(C) marks the point where the transistor turns off in the disturbed state.

The line (B)-(D) is the falling current in the undisturbed state. (D) is
where it hits zero.

The line (C)-(E) is the falling current in the disturbed state. (E) is
where it hits zero.


Do you now see the delay?

Sigh, you're barking up the wrong tree.

That's OK I'll play along.

Here's my picture again, I think it's nicer than yours.

____________ __________
___________| |________________|


/\
/ \
/ \
/ \
/ \
/ \
/ \
/ \
/ \
/ \ /
/ \ /
____________/ \_____/

<---Ton---><---Toff--->

You're operating discontinuously.

L2 is set through VIN and reset through VOUT.

Assume you have a PWM ramp with amplitude Vs and frequency Fs. Let's say
there is no offset and the error amplifier output voltage is Vcea.

Ton = Vcea/Fs.Vs

Ipk = VIN.Ton/L
= VIN.Vcea/Fs.Vs.L

The charge delivered to the output during Ton is

Qon = Ipk.Ton/2
= VIN(Vcea/Fs.Vs)^2/2L


Toff = Ipk.L/VOUT
= VIN.Ton.L/VOUT.L
= VIN.Ton/VOUT

The charge delivered to the output during Toff is

Qoff = Ipk.Toff/2
= Ipk.VIN.Ton/2VOUT
= Ipk.VIN.Vcea/2VOUT.Fs.Vs
= (VIN.Vcea/Fs.Vs.L)(VIN.Vcea/2VOUT.Fs.Vs)
= VIN^2(Vcea/Fs.Vs)^2/VOUT.2L

The total charge delivered to the output is

Qout = Qon + Qoff

The output current is the output charge times the switching frequency

Iout = Qout.Fs
= (VIN(Vcea/Fs.Vs)^2/2L + VIN^2(Vcea/Fs.Vs)^2/VOUT.2L).Fs
= Vcea^2(VIN/2L + VIN^2/VOUT.2L)/Fs.Vs^2
= Vcea^2.BUM

Where BUM = (VIN/2L + VIN^2/VOUT.2L)/Fs.Vs^2

Differentiate Iout with respect to Vcea....

dIout/dVcea = Vcea times half a BUM

Which is the small signal power circuit gain referred from the switch input
to the output.

Now, that's algebra..... and, it's the full picture.



I'll tell you where you keep on insisting in going wrong in the next
installment.

If you wish to ask......

DNA
 
K

Ken Smith

Newsgroups: sci.electronics.design
Subject: Re: Cuk converter bizzare control loop
Summary:
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Have taken the liberty of bring in the test from another part of this
thread because there are things in it that I'd like to point out to the OP
and others who are reading along at this point:


[... a lot of correct math deleted up to this point by DNA ...]
BUT all of that ignores the fact that the LCL section in a CUK converter
forms a resonant section which messes up the sums. Now I don't know how it
really messes up the sums but you are forced to close the loop below that
resonance if you are dealing with the input or output current, and there's
probably some sampled filter thing going on too.

DNA

For those who want more reading on the subject: try to find Advances In
Switch-Mode Power Conversion by R. D. Middlebrook and Slobodan Cuk. It
was published by TeslaCo in 1983.

I can tell you how to figure out where the poles land from the L1, L2 and
C1. The math isn't that hard.

The statement about the gain cross over having to be below that point is
wrong if the controller is current mode.

I'm about to make one more attempt to explaining the third item but I
think DNA is being intentionally as thick as two wet planks.

If you find Mr. Cuks works, look in Vol 1 and 2 on page 381 to see his
amplitude and phase vs frequency plots. Remember he is measuring from the
distrubance of the switching time to the output of the converter.

[...]
Sigh, you're barking up the wrong tree.

No, its you who's got the wrong end of this stick.

[..]

I'm going to try once more and then give up.

If you have a system, a portion of which is sampled, that you wish to
handle as a continuous small signal model, you must make some provision to
handle the the phase and frequency characteristics of the sampled portion.

If the sampled portion is linear and all frequencies under consideration
are below Nyquist, such a small signal model can be used.

All PWM converters are at least in part sampled systems. In the most
common type, the switching transistor is turned on at some fixed time
interval and the delay after that to when the transistor is turn off is
what is modulated to vary the output.

For this type of converter, the input to the PWM section is only sampled
at the time the transistor is turned off. To be more exact, the input in
some very narrow span of time is used because internally a ramp is being
compared to the input signal.

Once the converter has turned off the transistor, it can't turn it back on
until this cycle is completed and the next sampling of the input is only
done at the next time the transistor is turned off.

The rate that the current in the output inductor decreases, when the
transistor is off, is near enough to a straight line that we can assume a
straight line running down to zero. If a disturbance at the input of the
modulator caused the transistor to remain on for a slightly longer time,
this line is displaced upwards (ie a higher current) and intersects zero
at a later time.

This increased current in the inductor represents the effect of the
disturbance and most of it is at a time later than the sampling which
occured at the instant the transistor was shut off. This is proof that
there is a delay but it does not prove that the "transport dealy" model
best models this. I will now undertake that subject.

If the disturbance is assumed to be a sine wave at the input of the
modulator and is further assumed to be below Nyquist, there is no
mechanism by which the frequency of this waveform can effect the amount of
delay and therefor the delay must be constant. It is also obvious that
the amplitude of the resultant output current caused by the disturbance
is independant of the frequency of the disturbance. Therefor we have a
constant amplitude and constant delay time so the "transport delaY" model
is the correct one to use.
 
G

Genome

Ken Smith said:
Newsgroups: sci.electronics.design
Subject: Re: Cuk converter bizzare control loop
Summary:
Expires:
References: <jNntd.2501$x26.113@trndny03><[email protected]>
Sender:
Followup-To:
Distribution:
Organization:
Keywords:
Cc:

Have taken the liberty of bring in the test from another part of this
thread because there are things in it that I'd like to point out to the OP
and others who are reading along at this point:


[... a lot of correct math deleted up to this point by DNA ...]
BUT all of that ignores the fact that the LCL section in a CUK converter
forms a resonant section which messes up the sums. Now I don't know how it
really messes up the sums but you are forced to close the loop below that
resonance if you are dealing with the input or output current, and there's
probably some sampled filter thing going on too.

DNA

For those who want more reading on the subject: try to find Advances In
Switch-Mode Power Conversion by R. D. Middlebrook and Slobodan Cuk. It
was published by TeslaCo in 1983.

I can tell you how to figure out where the poles land from the L1, L2 and
C1. The math isn't that hard.

The statement about the gain cross over having to be below that point is
wrong if the controller is current mode.

I'm about to make one more attempt to explaining the third item but I
think DNA is being intentionally as thick as two wet planks.

If you find Mr. Cuks works, look in Vol 1 and 2 on page 381 to see his
amplitude and phase vs frequency plots. Remember he is measuring from the
distrubance of the switching time to the output of the converter.

[...]
Sigh, you're barking up the wrong tree.

No, its you who's got the wrong end of this stick.

[..]

I'm going to try once more and then give up.

If you have a system, a portion of which is sampled, that you wish to
handle as a continuous small signal model, you must make some provision to
handle the the phase and frequency characteristics of the sampled portion.

If the sampled portion is linear and all frequencies under consideration
are below Nyquist, such a small signal model can be used.

All PWM converters are at least in part sampled systems. In the most
common type, the switching transistor is turned on at some fixed time
interval and the delay after that to when the transistor is turn off is
what is modulated to vary the output.

For this type of converter, the input to the PWM section is only sampled
at the time the transistor is turned off. To be more exact, the input in
some very narrow span of time is used because internally a ramp is being
compared to the input signal.

Once the converter has turned off the transistor, it can't turn it back on
until this cycle is completed and the next sampling of the input is only
done at the next time the transistor is turned off.

The rate that the current in the output inductor decreases, when the
transistor is off, is near enough to a straight line that we can assume a
straight line running down to zero. If a disturbance at the input of the
modulator caused the transistor to remain on for a slightly longer time,
this line is displaced upwards (ie a higher current) and intersects zero
at a later time.

This increased current in the inductor represents the effect of the
disturbance and most of it is at a time later than the sampling which
occured at the instant the transistor was shut off. This is proof that
there is a delay but it does not prove that the "transport dealy" model
best models this. I will now undertake that subject.

If the disturbance is assumed to be a sine wave at the input of the
modulator and is further assumed to be below Nyquist, there is no
mechanism by which the frequency of this waveform can effect the amount of
delay and therefor the delay must be constant. It is also obvious that
the amplitude of the resultant output current caused by the disturbance
is independant of the frequency of the disturbance. Therefor we have a
constant amplitude and constant delay time so the "transport delaY" model
is the correct one to use.

Oh, so you didn't want to ask where you were going wrong.

You decided to go on your merry way and throw away what I said in the post
you were answering and insert some other stuff.

Harumph!

OK, I'll play too.

"Papers 14 and 15 return to converter modelling. In Paper 14, the
state-space averaging technique with inclusion of parasitics is used to show
that the storage-time modulation effect, first mentioned in Paper 5, leads
to increased filter damping for constant base drive to the power switch, but
to decreased damping for proportional drive. If the negative damping is
sufficient, an instability can result even for an open- loop converter. In
Paper 15, the Fourier analysis and modulator properties discussed in Paper 4
are separated, and results for two other modulators are given.

Contrary to some belief, the simple comparator type of modulator contributes
zero phase lag (transport delay) to the transfer function."



OK, now somewhere above you say......
For this type of converter, the input to the PWM section is only sampled
at the time the transistor is turned off.

This is where you keep on going wrong.

I hinted, and you snipped it.
I hinted again, and you snipped it.
I hinted once more..... and you snipped it.

Each time you snipped it you came back and said words/diagrams to the effect
of
For this type of converter, the input to the PWM section is only sampled
at the time the transistor is turned off.

And you are still doing it..... and you'll probably do it again.

Now,
For this type of converter, the input to the PWM section is only sampled
at the time the transistor is turned off.

Is wrong.

Think about it some more, ay?

DNA
 
K

Ken Smith

Genome said:
"Papers 14 and 15 return to converter modelling. In Paper 14, the
state-space averaging technique with inclusion of parasitics is used to show
that the storage-time modulation effect, first mentioned in Paper 5, leads
to increased filter damping for constant base drive to the power switch, but
to decreased damping for proportional drive. If the negative damping is
sufficient, an instability can result even for an open- loop converter. In
Paper 15, the Fourier analysis and modulator properties discussed in Paper 4
are separated, and results for two other modulators are given.

Contrary to some belief, the simple comparator type of modulator contributes
zero phase lag (transport delay) to the transfer function."

Who's papers?

Certainly not Cuk's as far as I can find
OK, now somewhere above you say......


This is where you keep on going wrong.

Ok, when it the input of the PWM circuit sampled if not at the time the
transistor is turned off. It certainly can't be later because the
transistor has already been switched at that time.

Is wrong.

Think about it some more, ay?

I've though about it quite a lot over the years and I still don't see
anyway that the PWM section can be sampling the input any later than when
it switches the transistor.
 
K

Ken Smith

I have been re-reading Mr. Cuk's book and it looks like I owe DNA an
apology. In Mr. Cuk's paper he does say that the "naturally sampled"
modulator has zero phase lag.

Unfortunately for DNA Mr Cuk also, on page 232, says that there is a RHP
zero in the Cuk converter due to "storage time modulation" and the
parasitic resistances. He may have to apologize to the other poster in
this thread who suggested that there was a RHP zero.

"storage time modulation" is an effect that is seen only when bipolar
devices are used as the switching device. This is a little odd because I
have seen an excess in phase shift at high frequencies with MOSFET
switches. I have always taken that as an experimental proof of the
transport delay of the system. If the RHP zero can appear and be large
enough with MOSFETs this would also give an excess phase and could be
close enough to appear to be the transport delay caused one.

BTW: the other post that I canceled was before this evenings reading.


Genome said:
Oh, so you didn't want to ask where you were going wrong.

You decided to go on your merry way and throw away what I said in the post
you were answering and insert some other stuff.

Harumph!

I think I may have deserved that. But I did read what you wrote before I
deleted it. The math appeared to me to only model the steady state case
in that it did not say anything about when the input was applied vs when
the result came out.


[...]
Contrary to some belief, the simple comparator type of modulator contributes
zero phase lag (transport delay) to the transfer function."

This is from the web site that is talking the books. In reading the book
you have to get to page 230 or so before you hit that issue.
 
C

ChrisGibboGibson

kensmith wrote:

[snip]
zero in the Cuk converter due to "storage time modulation" and the
parasitic resistances. He may have to apologize to the other poster in
this thread who suggested that there was a RHP zero.

But it was to be expected. Which is why I wrote...... "Loads of people will
argue with this. I don't care, they're wrong."

There *is* a RHP zero in a cuk converter. It isn't easy to spot, it doesn't
show up under simple analysis and many practical circuits seem to function
quite happily without correct compensation for it. But it's there. OPs circuit
is clearly one that *does* show it.

I remember the subject from uni. I also remember a lecturer showing quite
clearly that Cuk's original paper with the explanation for it being due to BJTs
as being wrong. It exists even with mosfets.

Now it may be sacriledge to say such a thing about Mr Cuk, but it's reality.
"storage time modulation" is an effect that is seen only when bipolar
devices are used as the switching device. This is a little odd because I
have seen an excess in phase shift at high frequencies with MOSFET
switches. I have always taken that as an experimental proof of the
transport delay of the system. If the RHP zero can appear and be large
enough with MOSFETs this would also give an excess phase and could be
close enough to appear to be the transport delay caused one.

Correct

Gibbo
 
G

Genome

Ken Smith said:
I have been re-reading Mr. Cuk's book and it looks like I owe DNA an
apology. In Mr. Cuk's paper he does say that the "naturally sampled"
modulator has zero phase lag.

[email protected] forging knowledge

Why?

Not because CUK says so....... Does he say why and does it make sense?

Why, as you understand it yourself, is there zero 'transport delay'?

Explain....

DNA
 
G

Genome

ChrisGibboGibson said:
kensmith wrote:

[snip]

"I remember the subject from uni. I also remember a lecturer showing quite
clearly that Cuk's original paper with the explanation for it being due to
BJTs as being wrong. It exists even with mosfets."

Something about the RHPZ in CUK converters.......



"I remember the subject from uni. I also remember a lecturer showing quite
clearly that Cuk's original paper with the explanation for it being due to
BJTs as being wrong. It exists even with mosfets."


Go on then..... if you think you're hard enough?

DNA
 
K

Ken Smith

Why?

Not because CUK says so....... Does he say why and does it make sense?

It seemed to latish in the evening. It conflicts with my other thoughs on
the subject. I will have to go through his text more carefully to make
sure that he is really talking about the same case as I am.

There is also some chance that he has made an error. The fact that his
RHP zero may explain the phase shifts I have seen, means that I can't
trust the fact that my observations and my theory seemed to agree.
 
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