Cuk converter bizzare control loop

[robert lafrance]

Right off the bat I will tell you this is homework - sorta. I got the thing
running pretty much ok. Used the old virtual decade box and it looks about
right. Now I just have to go back and analytically justify the loop that
works. Was supposed to finish this last problem in Mathcad, but Switchercad
works so nice.

With the thing running I see when I jerk the bus up and down the converter
kinda does opposite what I would expect. When I step it up to 550v from
450v the output actually goes down before catching itself and stabalizing.
I expect this is probably a characteristic of the species. This version
just uses output inductor in series with 10 ohm load. The problem is to get
it stable at 60Hz out. I'm just running along at DC out to satisfy my own
curiousity.

Would like to hear a comment on the control loop from someone who has played
with this animal.

Sorry I haven't been paying much attention to the group here. Started MSEE
program in September at UW Madison over the web. Last HW assignment in
progress. I would imagine lots of OT conversation (battle mode) weeks
before the election.

regards,
Bob

 

[Ken Smith]

Right off the bat I will tell you this is homework - sorta. I got the thing
running pretty much ok. Used the old virtual decade box and it looks about
right. Now I just have to go back and analytically justify the loop that
works. Was supposed to finish this last problem in Mathcad, but Switchercad
works so nice.

With the thing running I see when I jerk the bus up and down the converter
kinda does opposite what I would expect. When I step it up to 550v from
450v the output actually goes down before catching itself and stabalizing.
I expect this is probably a characteristic of the species. This version
just uses output inductor in series with 10 ohm load. The problem is to get
it stable at 60Hz out. I'm just running along at DC out to satisfy my own
curiousity.

Ascii art:


L1 * C1 * L2
-----)))))---------+-----!!----+----))))))-------
! !
!!- V C1
---!!- Q1 ---
!!- !
! !
GND GND


I assume that the circuit is this one. Notice how C1 provides a route
from the input side to the output side. A positive step on the input
tends to cause a positive step on the output. This should be no real
surprise.

At low frequencies of feedback, the duty cycle of Q1 determines the Vin to
Vout ratio. If you walk around the servo loop and add up all the gains
and phases, you can work out a Vode plot for the system. Depending on how
you PWM Q1, you may need to add a "transport delay" (exp(-ST)) to the
assumed transfer function to get it to match real life. The transport
delay usually has to be about 0.5 to 1 cycle of the PWM.

You can then prove this by inserting the disturbance on the spice model
and seeing what comes around the loop.

 

[ChrisGibboGibson]

Right off the bat I will tell you this is homework - sorta. I got the thing
running pretty much ok. Used the old virtual decade box and it looks about
right. Now I just have to go back and analytically justify the loop that
works. Was supposed to finish this last problem in Mathcad, but Switchercad
works so nice.

With the thing running I see when I jerk the bus up and down the converter
kinda does opposite what I would expect. When I step it up to 550v from
450v the output actually goes down before catching itself and stabalizing.
I expect this is probably a characteristic of the species. This version
just uses output inductor in series with 10 ohm load. The problem is to get
it stable at 60Hz out. I'm just running along at DC out to satisfy my own
curiousity.

Would like to hear a comment on the control loop from someone who has played
with this animal.

Look up "right half plane zero". As you suspect it is a "feature* of the
species. It ocurrs in continuous mode mode only. Run it in discontinuous mode
(complete energy transfer) and the problem will go away. Despite what you might
read in some texts there's piss all you can do about it other than to swamp it
by drastically reducing the bandwidth of the loop. This can be proved
mathematically.

Best analogy I ever heard for a right half plane zero was on this NG. Think
about turning a bicycle.

Loads of people will argue with this. I don't care, they're wrong. I'm off to
the airport to fly to USA.

Gibbo

 

[Yzordderrex]

Ok, thanks Ken. I'll play around some more. It is acting a little
contrary to what I would expect in that a step up in voltage causes it
to reduce the output. I expect if I zoom in I'll see the FB signal
overshoot, which is then causing the dip. Prof only wants the thing
to run a 60Hz sinewave, so homework done.

regards,
Bob

 

[Yzordderrex]

Ok, thanks Ken. I'll play around some more. It is acting a little
contrary to what I would expect in that a step up in voltage causes it
to reduce the output. I expect if I zoom in I'll see the FB signal
overshoot, which is then causing the dip. Prof only wants the thing
to run a 60Hz sinewave, so homework done.

regards,
Bob

 

[Genome]

Right off the bat I will tell you this is homework - sorta. I got the thing
running pretty much ok. Used the old virtual decade box and it looks about
right. Now I just have to go back and analytically justify the loop that
works. Was supposed to finish this last problem in Mathcad, but Switchercad
works so nice.

With the thing running I see when I jerk the bus up and down the converter
kinda does opposite what I would expect. When I step it up to 550v from
450v the output actually goes down before catching itself and stabalizing.
I expect this is probably a characteristic of the species. This version
just uses output inductor in series with 10 ohm load. The problem is to get
it stable at 60Hz out. I'm just running along at DC out to satisfy my own
curiousity.

Would like to hear a comment on the control loop from someone who has played
with this animal.

Sorry I haven't been paying much attention to the group here. Started MSEE
program in September at UW Madison over the web. Last HW assignment in
progress. I would imagine lots of OT conversation (battle mode) weeks
before the election.

regards,
Bob

Hmmmm... I'd guess you are doing some form of PFC and controlling switch
current to avoid the LC resonance.

Your current loop will be quite fast but your voltage loop, if that's what's
dealing with the output will be quite slow.

Switch current is the sum of input and output current multiplied by the
operating duty cycle which averages to input current.

That's nice for PFC because you want to control input current.

However.

If you wack the input voltage up with your slow voltage loop demanding what
is effectively a fixed switch current.....

The input current will stomp up and the current loop, being fast, will spot
it and adjust things so the switch current, sum of input and output current,
remains the same and so the output current will drop.

So the output voltage will drop and, sometime later, the voltage loop will
realise this and bring things back into regulation.

If you've used a proper PFC IC then the VFF multiplier should take care of
it.... but it's filtered to buggery to avoid line current distortion so it
doesn't.


IN THE MEANTIME

I'd just like to point out that a CUK converter doesn't suffer a transport
delay and it doesn't suffer from a right half plane zero.

Ken Smith and ChrisGibboGibson are blowing it out of their collective
Assholes.

DNA

 

[Larry Brasfield]

[to OP]
That is prima facie evidence of the right half plane zero. So don't let
anybody tell you it is not there. It is, and this is a well known fact.

[to OP]
I used a convertor with the same response to convey signals at
frequencies approaching a small submultiple of the switching
frequency. This used a compensating zero in the right half plane.

Look up "right half plane zero". As you suspect it is a "feature* of the
species. It ocurrs in continuous mode mode only.

So far, so good.

Run it in discontinuous mode
(complete energy transfer) and the problem will go away. Despite what you might
read in some texts there's piss all you can do about it other than to swamp it
by drastically reducing the bandwidth of the loop. This can be proved
mathematically.

That, I disagree with, having done much better than that, both
analytically and in practise. If not for the effects that occur as
the response approaches the switching frequency, you could
bring the response poles arbitrarily to the left.

Best analogy I ever heard for a right half plane zero was on this NG. Think
about turning a bicycle.

Not a bad analogy. Think about balancing an upside down pendulum.
It is the same problem with respect to balancing the bike.

Loads of people will argue with this. I don't care, they're wrong. I'm off to
the airport to fly to USA.

Good luck.

 

[Terry Given]

:

[to OP]
That is prima facie evidence of the right half plane zero. So don't let
anybody tell you it is not there. It is, and this is a well known fact.



[to OP]
I used a convertor with the same response to convey signals at
frequencies approaching a small submultiple of the switching
frequency. This used a compensating zero in the right half plane.

Look up "right half plane zero". As you suspect it is a "feature* of the
species. It ocurrs in continuous mode mode only.

So far, so good.

Run it in discontinuous mode
(complete energy transfer) and the problem will go away. Despite what you might
read in some texts there's piss all you can do about it other than to swamp it
by drastically reducing the bandwidth of the loop. This can be proved
mathematically.

That, I disagree with, having done much better than that, both
analytically and in practise. If not for the effects that occur as
the response approaches the switching frequency, you could
bring the response poles arbitrarily to the left.

Best analogy I ever heard for a right half plane zero was on this NG. Think
about turning a bicycle.

Not a bad analogy. Think about balancing an upside down pendulum.
It is the same problem with respect to balancing the bike.

and a well-tuned inverted penulum contoller will of course move bacwards
initially in response to a "move forward" command. This tips the
pendulum in the direction of desired motion, and the cart then moves to
keep it from falling

Good luck.

Cheers
Terry

 

[Genome]

IN THE MEANTIME

I'd just like to point out that a CUK converter doesn't suffer a transport
delay and it doesn't suffer from a right half plane zero.

Ken Smith and ChrisGibboGibson are blowing it out of their collective
Assholes.

DNA

Oh, Larry Brasfield is blowing big chunks as well.

DNA

 

[Ken Smith]

IN THE MEANTIME

I'd just like to point out that a CUK converter doesn't suffer a transport
delay and it doesn't suffer from a right half plane zero.

Yes it does have transport delay as I said including the qualifier about
how you are doing the PWM control[1]. Since you have demonstated that you
don't know that much, I'll let others decide if your word can be trusted
about the RHP zero.

[1] go read my post elsewhere in this thread.

 

[Genome]

IN THE MEANTIME

I'd just like to point out that a CUK converter doesn't suffer a transport
delay and it doesn't suffer from a right half plane zero.

Yes it does have transport delay as I said including the qualifier about
how you are doing the PWM control[1]. Since you have demonstated that you
don't know that much, I'll let others decide if your word can be trusted
about the RHP zero.

[1] go read my post elsewhere in this thread.

OK Ken, it's a CUK..... not a SEPIC.

I know it's a CUK because he said it was a CUK and a CUK doesn't suffer from
a transport delay or a right half plane zero. Fair enough, a SEPIC does, but
this is a CUK, not a SEPIC.

DNA

 

[Yzordderrex]

Seems I've gotten a lot of milage out of this post.

I don't think it has a RHP zero either. Just a bunch of poles in
about the same place which drives the transfer function bonkers. Looks
like this model has got some Q as well - some peaky gain where all the
poles are. Gain then drops like a rock. I'll agree the way to get
this thing to behave is to stick another pole in front of the rest of
em and drive the gain/bandwidth down early. I would inviite my
professor here to offer his take on it, but somebody might offend him.
This used to be such a polite place to visit. Heheh.

Meanwhile I will study for final and perhaps spend a few more hours in
the analytical mode here with master Cuk. If I develope a thesis I
will be sure to post.

thanks all
Bob


regards,
Bob

 

[Genome]

Seems I've gotten a lot of milage out of this post.

I don't think it has a RHP zero either. Just a bunch of poles in
about the same place which drives the transfer function bonkers. Looks
like this model has got some Q as well - some peaky gain where all the
poles are. Gain then drops like a rock. I'll agree the way to get
this thing to behave is to stick another pole in front of the rest of
em and drive the gain/bandwidth down early. I would inviite my
professor here to offer his take on it, but somebody might offend him.
This used to be such a polite place to visit. Heheh.

Meanwhile I will study for final and perhaps spend a few more hours in
the analytical mode here with master Cuk. If I develope a thesis I
will be sure to post.

thanks all
Bob


regards,
Bob

Replace your capacitor with a voltage source of (VIN+VOUT) because that's
what it charges up to.

Call your inductors L1 and L2, make them the same, L.

Turn your switch on.

L1 and L2 are set through VIN.Ton

Turn your switch off

L1 and L2 are reset through VOUT.Toff

Call Ton D and Toff (1-D)

Steady state the setting and resetting volt seconds remain the same so

VIN.D = VOUT(1-D)
= VOUT-VOUT.D

Rearrange and

D = VOUT/(VIN+VOUT)

Perturb the duty cycle, D, by a small amount, p.

D goes to (D+p)
(1-D) goes to (1-D-p)

Which places a net change in the voltage across the inductors of

dVL = VIN(D+p)-VOUT(1-D-p)
= VIN.D + VIN.p - VOUT + VOUT.D + VOUT.p
= (VIN+VOUT)D - VOUT +(VIN+VOUT)p

Substitute for D and some bits dissapear

dVL = (VIN+VOUT)p

The change in voltage across the inductor(s) results in a change in current
through them.

dIL = dVL/XL
= -j(VIN+VOUT)p/2pifL

Then you have to work out where the perturbation came from in the first
place.

Referred to input and output you get

dIL = -j(VIN+VOUT)p/2pifL

Referred to switch current dIL is sampled by the duty cycle and the dIL in
both inductors is measured so.....

dIsw = -j2D(VIN+VOUT)p/2pifL

BUT........ the perturbation also 'samples' the steady state inductor
currents so

dIsw = -j2D(VIN+VOUT)p/2pifL + p(IIN + IOUT)

Substitute for D and

dIsw = -jVOUTp/pifL + p(IIN+IOUT)
= p[-jVOUT/pifL+(IIN+IOUT)]

Which is a DC pole with a left hand plane zero.


BUT all of that ignores the fact that the LCL section in a CUK converter
forms a resonant section which messes up the sums. Now I don't know how it
really messes up the sums but you are forced to close the loop below that
resonance if you are dealing with the input or output current, and there's
probably some sampled filter thing going on too.

DNA

 

[Ken Smith]

IN THE MEANTIME

I'd just like to point out that a CUK converter doesn't suffer a transport
delay and it doesn't suffer from a right half plane zero.

Yes it does have transport delay as I said including the qualifier about
how you are doing the PWM control[1]. Since you have demonstated that you
don't know that much, I'll let others decide if your word can be trusted
about the RHP zero.

[1] go read my post elsewhere in this thread.

OK Ken, it's a CUK..... not a SEPIC.

I know it's a CUK because he said it was a CUK and a CUK doesn't suffer from
a transport delay or a right half plane zero. Fair enough, a SEPIC does, but
this is a CUK, not a SEPIC.

No, a Cuk does have transport delay, or at least that is how you model it
if you treat it as a small signal linear system.

The PWM method has a delay from the information on its input to the energy
appearing at the output. Assume discontinuous mode: The current in the
output inductor has to ramp up to its peak value. The energy output is
only done after the current has ramped up and then back down. This means
that the energy is delived after the information on the input is used
making a phase delay. There is no amplitude reduction to go along with
this phase delay and the phase shift is linear with frequency so it looks
just like a transport delay.

I'm not going talk about the RHP zero. It wasn't my issue.

 

[Ken Smith]

Seems I've gotten a lot of milage out of this post.

I don't think it has a RHP zero either. Just a bunch of poles in
about the same place which drives the transfer function bonkers. Looks
like this model has got some Q as well - some peaky gain where all the
poles are. Gain then drops like a rock. I'll agree the way to get
this thing to behave is to stick another pole in front of the rest of
em and drive the gain/bandwidth down early. I would inviite my
professor here to offer his take on it, but somebody might offend him.
This used to be such a polite place to visit. Heheh.

You are better to use a pole-zero-pole combination. Basically you make a
P+I controller and then add another pole to keep switching noise out of
things. This way you can make the gain cross-over point at perhaps twice
the frequency you could do otherwise.

 

[Ken Smith]

BUT all of that ignores the fact that the LCL section in a CUK converter
forms a resonant section which messes up the sums.

Look at it this way:


L1 C1 L1
+V ---))))))-------+-------!!------+-----((((((----- -V
in ! ! out
o o
/ S1 / S2
! !
GND GND



Assume the switching frequency is way above the disturbance.

Disturbing Vout, holding the duty cycle constant and working out the
effect on the "average" voltage at S2 and S1 is easier than working from
the duty cycle out to each end.

 

[Genome]

[...]
IN THE MEANTIME

I'd just like to point out that a CUK converter doesn't suffer a transport
delay and it doesn't suffer from a right half plane zero.

Yes it does have transport delay as I said including the qualifier about
how you are doing the PWM control[1]. Since you have demonstated that you
don't know that much, I'll let others decide if your word can be trusted
about the RHP zero.

[1] go read my post elsewhere in this thread.

OK Ken, it's a CUK..... not a SEPIC.

I know it's a CUK because he said it was a CUK and a CUK doesn't suffer from
a transport delay or a right half plane zero. Fair enough, a SEPIC does, but
this is a CUK, not a SEPIC.

No, a Cuk does have transport delay, or at least that is how you model it
if you treat it as a small signal linear system.

The PWM method has a delay from the information on its input to the energy
appearing at the output. Assume discontinuous mode: The current in the
output inductor has to ramp up to its peak value. The energy output is
only done after the current has ramped up and then back down. This means
that the energy is delived after the information on the input is used
making a phase delay. There is no amplitude reduction to go along with
this phase delay and the phase shift is linear with frequency so it looks
just like a transport delay.

I'm not going talk about the RHP zero. It wasn't my issue.

When the switch is on one end of the coupling capacitor is grounded and its
other end is driven to -(VIN+VOUT). The output diode is reverse biased and
the output inductor is being set through VIN with its current flowing in the
output load, it is always connected to the load. There is no delay.

DNA

 

[Yzordderrex]

Yes, I think the pole zero pole might be best. I'll give it a try and
see.

thanks again everybody.

regards
Bob

 

[Ken Smith]

When the switch is on one end of the coupling capacitor is grounded and its
other end is driven to -(VIN+VOUT). The output diode is reverse biased and
the output inductor is being set through VIN with its current flowing in the
output load, it is always connected to the load. There is no delay.

Let me draw you a picture of what I said. It may be clearer:

.............................................
.............................................
....------------............................. Switching
---........--------------------------------- Times
............:..:...........:.................
............:..*...........:.................
............:.*:*..........:.................
............:*.:.*.........:.................
............*..:..*........:................. L2
...........*:*.:...*.......:................. Current
..........*.:.*:....*......:.................
.........*..:..*.....*.....:.................
........*...:..:*.....*....:.................
.......*....:..:.*.....*...:.................
......*.....:..:..*.....*..:.................
.....*......:..:...*.....*...................
....*.......:..:....*.....*:.................
***........:..:.....************************
............:..:...........:.................
: : :
T1 >: :< :
: :
:<---- T2 ---->:


All the information comes from the T1 time. The eneergy is delivered
during T2. Since the mid point of T2 is after the mid point of T1, there
is a delay. If you are goinf to treat the system as a linear continuous
system to solve for stablility, you have to include a transport delay to
handle the lag from T1 to T2.

Got it now?

 

[Genome]

Let me draw you a picture of what I said. It may be clearer:

............................................
............................................
...------------............................. Switching
---........--------------------------------- Times
...........:..:...........:.................
...........:..*...........:.................
...........:.*:*..........:.................
...........:*.:.*.........:.................
...........*..:..*........:................. L2
..........*:*.:...*.......:................. Current
.........*.:.*:....*......:.................
........*..:..*.....*.....:.................
.......*...:..:*.....*....:.................
......*....:..:.*.....*...:.................
.....*.....:..:..*.....*..:.................
....*......:..:...*.....*...................
...*.......:..:....*.....*:.................
***........:..:.....************************
...........:..:...........:.................
: : :
T1 >: :< :
: :
:<---- T2 ---->:


All the information comes from the T1 time. The energy is delivered
during T2. Since the mid point of T2 is after the mid point of T1, there
is a delay. If you are going to treat the system as a linear continuous
system to solve for stablility, you have to include a transport delay to
handle the lag from T1 to T2.

Got it now?

Nope

____________ __________
___________| |________________|


/\
/ \
/ \
/ \
/ \
/ \
/ \
/ \
/ \
/ \ /
/ \ /
____________/ \_____/

<----T1----><----T2---->

You must bear in mind that current in L2 is 'output' current, the inductor
is connected to the output. Current (Energy) is flowing in the inductor, and
the output, during 'both' T1 AND T2.

As per your previous schematic,

L1 * C1 * L2
,-----)))))---------,-----||----,----))))))-------,
| | | |
| | | |
| ||- V |
VIN ---||- Q1 --- VOUT
| ||- | |
| | | |
'-------------------'-----------'-----------------'
|
GND

L2 is connected directly to VOUT.

In a SEPIC the diode and L2 are swapped. Under those circumstances energy is
only delivered during switch off time (which is what you appear to be
applying a CUK) and you suffer a RHPZ and the transport delay.

Your description of the CUK sounds more like you are thinking about a SEPIC.


DNA