CMOS analogues switch capacitance

[Chris Jones]

John, _Very_good_suggestion_!

The only relatively constant term would be gate capacitance, ESD and
MOS body diode capacitances will be all over the place with
temperature.

...Jim Thompson

One other thing (that you would know well) is that the gate capacitance of
the MOS devices will depend strongly on the bias (VGS) so it is important
to measure the calibration channel and the measurement channel with the
same DC bias and about the same signal amplitude on the switch pins.

Chris

 

[Jim Thompson]

Jim Thompson wrote:
[snip]

The only relatively constant term would be gate capacitance, ESD and
MOS body diode capacitances will be all over the place with
temperature.

...Jim Thompson

One other thing (that you would know well) is that the gate capacitance of
the MOS devices will depend strongly on the bias (VGS) so it is important
to measure the calibration channel and the measurement channel with the
same DC bias and about the same signal amplitude on the switch pins.

Chris

Nope. I've modeled that situation very carefully. Once a channel is
induced, the gate _capacitance_ is essentially a constant, only the
series resistance varies which, of course, can screw you up royally if
you aren't aware of it.

Now that I have it characterized I've been using gate capacitance as
bypass capacitors extensively.

...Jim Thompson

 

[Jim Thompson]

Hello Chris,


Another thing to watch is the substrate, for chips where it is brought
out to a pin. During many of my consulting trips I found that much of
the grief was rooted there. The substrate was connected to "somewhere"
and in one case the pin was left open...

Ah, Yes! The floating body syndrome ;-)

...Jim Thompson

 

[Joerg]

Hello Jim,

Ah, Yes! The floating body syndrome ;-)

What floored me was the rationale behind it: "But we only need input,
output and control signal".

The topper of all unconnected things (grounds in that case) was when a
sample-gate mixer was squealing and gurgling. I told them that shortwave
stations were getting in because there isn't a ground structure. "Yeah,
right. And they want to talk to us from outer space". Moved the L.O.
registers a bit and BBC World Service came out of the speaker nice and
clear...

 

[Jim Thompson]

Hello Jim,


What floored me was the rationale behind it: "But we only need input,
output and control signal".

The topper of all unconnected things (grounds in that case) was when a
sample-gate mixer was squealing and gurgling. I told them that shortwave
stations were getting in because there isn't a ground structure. "Yeah,
right. And they want to talk to us from outer space". Moved the L.O.
registers a bit and BBC World Service came out of the speaker nice and
clear...

I didn't come up with it myself, but one of the more clever things
I've seen is for HV and power-off tolerant inputs and outputs... the
body of the P-channel ESD device is disconnected using a switch ;-)

...Jim Thompson

 

[Chris Jones]

Jim Thompson wrote:
[snip]

The only relatively constant term would be gate capacitance, ESD and
MOS body diode capacitances will be all over the place with
temperature.

...Jim Thompson

One other thing (that you would know well) is that the gate capacitance of
the MOS devices will depend strongly on the bias (VGS) so it is important
to measure the calibration channel and the measurement channel with the
same DC bias and about the same signal amplitude on the switch pins.

Chris

Nope. I've modeled that situation very carefully. Once a channel is
induced, the gate _capacitance_ is essentially a constant, only the
series resistance varies which, of course, can screw you up royally if
you aren't aware of it.

Now that I have it characterized I've been using gate capacitance as
bypass capacitors extensively.

...Jim Thompson

Right, mos devices are nice dense decoupling capacitors, but they are also
used as the varactors in RF VCOs because the capacitance from gate to
source and drain is much greater when the channel is formed than the
capacitance when the channel is not formed. What I was suggesting is that
if the drain/source terminals are very close to the positive supply voltage
then the NMOS device will be on and the PMOS device will be off, whereas
when the source & drain pins are near the negative rail, then the PMOS
device will be on and the NMOS device will be off. Because the PMOS device
has probably the same oxide thickness but at least double the width of the
NMOS device, I would expect that the capacitance would be substantially
more when the PMOS device is on than when only the NMOS device is on, and
highest of all when both devices are on. Another thing that I have not yet
considered is that many analog switch ICs selectively drive the backgate
from either the supply rail or the S/D terminals (and hence have lousy
charge injection). Depending on how they do this, all sorts of odd things
might happen, which you would be in a better position to comment on I
expect.

Chris

 

[Chris Jones]

Jim Thompson wrote:
[snip]

The only relatively constant term would be gate capacitance, ESD and
MOS body diode capacitances will be all over the place with
temperature.

...Jim Thompson


One other thing (that you would know well) is that the gate capacitance
of the MOS devices will depend strongly on the bias (VGS) so it is
important to measure the calibration channel and the measurement channel
with the same DC bias and about the same signal amplitude on the switch
pins.

Chris

Nope. I've modeled that situation very carefully. Once a channel is
induced, the gate _capacitance_ is essentially a constant, only the
series resistance varies which, of course, can screw you up royally if
you aren't aware of it.

Now that I have it characterized I've been using gate capacitance as
bypass capacitors extensively.

...Jim Thompson

Right, mos devices are nice dense decoupling capacitors, but they are also
used as the varactors in RF VCOs because the capacitance from gate to
source and drain is much greater when the channel is formed than the
capacitance when the channel is not formed. What I was suggesting is that
if the drain/source terminals are very close to the positive supply
voltage then the NMOS device will be on and the PMOS device will be off,
whereas when the source & drain pins are near the negative rail, then the
PMOS
device will be on and the NMOS device will be off.

OOPS!!! other way around, but you get what I mean....

[snip]

 

[joseph2k]

No, but the gate capacitance varies trivially compared to the
surrounding junctions.

...Jim Thompson

There is another issue with CMOS switches operating in low noise or high
speed applications. It is not really like capacitance but produces similar
effects, it is charge injection. Charge injection is relatively free of
temperature effects, but varies some with input voltage and supply voltage.
Have you had to design to control it?

 

[Jim Thompson]

Jim Thompson wrote:
[snip]

....the gate capacitance varies trivially compared to the
surrounding junctions.

...Jim Thompson

There is another issue with CMOS switches operating in low noise or high
speed applications. It is not really like capacitance but produces similar
effects, it is charge injection. Charge injection is relatively free of
temperature effects, but varies some with input voltage and supply voltage.
Have you had to design to control it?

Yes ;-)

...Jim Thompson

 

[Joerg]

Hello Joseph,

There is another issue with CMOS switches operating in low noise or high
speed applications. It is not really like capacitance but produces similar
effects, it is charge injection. Charge injection is relatively free of
temperature effects, but varies some with input voltage and supply voltage.
Have you had to design to control it?

I guess anybody who ever designed samplers has. It's not always fun
though, especially when you find out like I did a few years ago that
your favorite quad array has been priced out of the typical BOM budget
range :-(

However, there is another architecture that seems to not be taught
anymore at the colleges: Four fast diodes and a toroid transformer.
Ideally a quad but many of those have become expensive/unobtainium so I
usually try to get away with pairs. That reduces Ci effects down to
almost zilch.

 

[Jim Thompson]

Hello Joseph,


I guess anybody who ever designed samplers has. It's not always fun
though, especially when you find out like I did a few years ago that
your favorite quad array has been priced out of the typical BOM budget
range :-(

However, there is another architecture that seems to not be taught
anymore at the colleges: Four fast diodes and a toroid transformer.
Ideally a quad but many of those have become expensive/unobtainium so I
usually try to get away with pairs. That reduces Ci effects down to
almost zilch.

Hard to integrate though ;-)

...Jim Thompson

 

[Joerg]

Hello Jim,

Hard to integrate though ;-)

Yes, even hard to buy. Making the transformer is an art, almost like
tuning a vintage Alfa Romeo (oh, only Giuseppe can do that...). They are
tiny and the wires have to be arranged just so, then push them with a
tooth pick until you see the notch on the scope right there, then pot it
up. But the performance of such samplers is astounding.