Wise up and cope? What an asshole!
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Brushing up on theory: Butterworth LCR filter design?
Wise up and cope? What an asshole!
K
krw
We're using some of those (don't believer they're TDK) to isolate RF
buzz (from frequency hopping) from the power supply on some
replacement[*] headphone drivers. They've been known to cause as many
problems as they solve. The footprint isn't exactly an 0805 (center
ground stripe) so bridging across them can be a problem.
[*] Replacement part required because of ROHS, of course.
Yeesh, Jim, I haven't looked at this newsgroup since roadrunner
dropped NNTP support. I've missed the chaos and ignorance... You need
to thump some of the empty heads.
Anyway, about charge conservation in circuit simulation: The problem
was always with MOSFETs. BJTs and diodes were fine from the original
SPICE1 code -- if you start with a q(v) equation and differentiate it
to get capacitance, things are surprisingly good. Path integrals work
out... The problem was the Meyer model for channel capacitance, used
in the MOS level 1, 2, 3 models (and others). The model described the
capacitances and did a numerical estimation of charge based on them.
This was just plain wrong, since they're trying to estimate, e.g., qg
(vd,vg,vs,vb) without an integrable function. A good exposition of the
problem and first practical fix was in Ping Yang's 1983 paper.
So, MOS levels 1, 2, 3 are probably still wrong in SPICE -- I haven't
looked lately. Any of the more recent models, BSIM3, BSIM4, EKV, PSP,
all start with q(v) and differentiate to get the (non-reciprocal)
capacitances, so they're more-or-less correctly set up for charge
conservation by construction. For transient analysis, even if they
get the differentiation wrong, as long as q(v) is correct the model
will conserve charge -- if it converges.
For the picky, yes there will be some error on each cycle due to
convergence tolerances. If the simulator you're using properly
implements truncation error timestep control, the loss will be minimal
and controllable by tightening reltol and chgtol. If you're using
certain 'gold standard' simulators, you'll probably have trouble
unless you're some kind of prescient in figuring the right model
switches and options. My simulator does quite well.
--Steve
dropped NNTP support. I've missed the chaos and ignorance... You need
to thump some of the empty heads.
Anyway, about charge conservation in circuit simulation: The problem
was always with MOSFETs. BJTs and diodes were fine from the original
SPICE1 code -- if you start with a q(v) equation and differentiate it
to get capacitance, things are surprisingly good. Path integrals work
out... The problem was the Meyer model for channel capacitance, used
in the MOS level 1, 2, 3 models (and others). The model described the
capacitances and did a numerical estimation of charge based on them.
This was just plain wrong, since they're trying to estimate, e.g., qg
(vd,vg,vs,vb) without an integrable function. A good exposition of the
problem and first practical fix was in Ping Yang's 1983 paper.
So, MOS levels 1, 2, 3 are probably still wrong in SPICE -- I haven't
looked lately. Any of the more recent models, BSIM3, BSIM4, EKV, PSP,
all start with q(v) and differentiate to get the (non-reciprocal)
capacitances, so they're more-or-less correctly set up for charge
conservation by construction. For transient analysis, even if they
get the differentiation wrong, as long as q(v) is correct the model
will conserve charge -- if it converges.
For the picky, yes there will be some error on each cycle due to
convergence tolerances. If the simulator you're using properly
implements truncation error timestep control, the loss will be minimal
and controllable by tightening reltol and chgtol. If you're using
certain 'gold standard' simulators, you'll probably have trouble
unless you're some kind of prescient in figuring the right model
switches and options. My simulator does quite well.
--Steve
J
JosephKK
Speaking to and of your self i see.
Yeesh, Jim, I haven't looked at this newsgroup since roadrunner
dropped NNTP support. I've missed the chaos and ignorance... You need
to thump some of the empty heads.
Anyway, about charge conservation in circuit simulation: The problem
was always with MOSFETs. BJTs and diodes were fine from the original
SPICE1 code -- if you start with a q(v) equation and differentiate it
to get capacitance, things are surprisingly good. Path integrals work
out... The problem was the Meyer model for channel capacitance, used
in the MOS level 1, 2, 3 models (and others). The model described the
capacitances and did a numerical estimation of charge based on them.
This was just plain wrong, since they're trying to estimate, e.g., qg
(vd,vg,vs,vb) without an integrable function. A good exposition of the
problem and first practical fix was in Ping Yang's 1983 paper.
So, MOS levels 1, 2, 3 are probably still wrong in SPICE -- I haven't
looked lately. Any of the more recent models, BSIM3, BSIM4, EKV, PSP,
all start with q(v) and differentiate to get the (non-reciprocal)
capacitances, so they're more-or-less correctly set up for charge
conservation by construction. For transient analysis, even if they
get the differentiation wrong, as long as q(v) is correct the model
will conserve charge -- if it converges.
For the picky, yes there will be some error on each cycle due to
convergence tolerances. If the simulator you're using properly
implements truncation error timestep control, the loss will be minimal
and controllable by tightening reltol and chgtol. If you're using
certain 'gold standard' simulators, you'll probably have trouble
unless you're some kind of prescient in figuring the right model
switches and options. My simulator does quite well.
--Steve
But my point was you couldn't use spice for high accuracy, such as
SCFs, which is why switcap was invented in the first place.
I really don't understand Jim negative comments about me, but trust
me, I've delivered silicon. Then again, when it comes to Jim, you have
to look at the source and just shrug it off as some jerk.
Oh, are you telling me your are rubber and I'm glue. Hey, that's
really telling me. Oh boy.
Charge redistribution circuits go through many cycles, so the error
can accumulate. Like a said many posts ago, you would see this is
cyclic converters.
In the NMOS days (yeah, I'm that old), there was great effort into
studying this charge error since you didn't have complimentary
switches. Dummy switch schemes were tried in spice and silicon with
little correlation.
J
Jeroen Belleman
"complementary"
OK, you win. ;-)
K
krw
The ones we use are from MuRata (NFL18ST).
When you say it's coming "out of" the FPGA... How? Power? Signal
pins? Air? In any case it is weird. Did you ask Xilinx about it?
The filters were making my output driver (LM7171 DSL driver used in
a Howland current pump) oscillate at 160MHz and suck gobs of power.
Bridging them with a zero ohm resistor eliminated the problem, but
as I said, it can be tricky with the ground stripe in the middle.
R
Rich Grise
On Jan 21, 8:02 pm, [email protected] wrote: [snip]My simulator does quite well.
--Steve
No. SWITCAP is much faster.
I guarantee I've delivered _far_more_ WORKING silicon than you.
You said the simulator didn't conserve charge. You were wrong. I
know you have a lot of trouble admitting you're wrong. Get over it,
JERK!
...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona 85048 Skype: Contacts Only | |
| Voice
| E-mail Icon athttp://www.analog-innovations.com| 1962 |
It's what you learn, after you know it all, that counts.
You certainly deliver more bullshit than I do.
J
JosephKK
Your twisted misrepresentations are on you.
J
JosephKK
Makes me wonder about internal frequency multipliers leaking somehow.
K
krw
If the frequency multipliers were leaking it would have to be at a
multiple of the input clock. John indicated there is no (obvious)
numerical relation.
I'm sticking my fingers in my ears and saying "Nah nah nah I can't
hear you."
J
JosephKK
Who constrained the frequency ratios to integer? Not i. Any rational
ratio is reasonable. Alternatively there would have to be free
running oscillations, with whatever causes they may have. The
frequencies were noted for being stable were they not?
K
krw
The frequencies bear no resemblance to the output either. Do you
think there is a random rogue multiplier with an antenna on it? Note
that John said there is "no obvious numerical relation to ANY clocks".
