Arduino control of model train signalling (was: LED Power Supply for Control Panel)

P4 Modeller · Nov 5, 2013

No Probs Steve.

Have busied myself building a semaphore signal and mount for servo.
Good to get some hands on modelling

Guess thats the next project that hopefully won't need to bother you with

Mark

(*steve*) · Nov 10, 2013

I'm looking at this again.

It looks like we're going backwards again. We don't have plain states and transitions any more. I'm not sure what has happened.

edit: Ignore me, I'm embarrassing myself. I know what I'm looking at now.

(*steve*) · Nov 11, 2013

OK, I've written a program to emulate your state machine.

In doing so, I found a few errors in your states and transitions, mostly small and easily fixed. In general they fell into one of 3 categories:

1) Mentioning the wrong panel
2) Typo or alternate spellings of signals, inputs, outputs, etc.
3) lack of setting output signals.

If you can PM me your email address, I'll email you a program which shows you the four panels ad allows you to activate them and exercise the state machines.

Following is the important part of the implementation which encodes your rules. Ignore the fact it's not in C, the general structure should look familiar.

The basic things to know are:

1) A switch statement in C is a case statement in this language.
2) a function in C is a procedure in this language
3) braces { ...} are replaced with begin ... end
4) = is used for comparison, := is used for assignment (replaces == and =)
5) variables are defined as "name : type;", rather than "type name;"
6) I'm not showing you all the code -- in particular many of the definitions are omitted for clarity.

CFY_UD Panel

Code:

const
  S_CFY_UD_S_INIT = 0;
  S_CFY_UD_S_RSIE = 1;
  S_CFY_UD_S_SDIC = 2;
  S_CFY_UD_S_SAIE = 3;
  S_CFY_UD_S_FDIC = 4;
  S_CFY_UD_S_FRSE = 5;
  S_CFY_UD_S_FAIL = 6;

implementation

{$R *.dfm}

uses
  fERM_UA,
  fERM_UD,
  fLFY_UA;

procedure TfrmCFY_UD.btnStepClick(Sender: TObject);
begin
  ProcessTransitions;
end;

procedure TfrmCFY_UD.ProcessTransitions;
var
  iState: integer;
begin
  iState := cmbState.ItemIndex; // get the current state

  // no see if we can transition to another state
  case iState of
    S_CFY_UD_S_INIT: { 0 }
      Begin
        if chkCFY_UD_I_ANS.Checked then
        begin
          GoToState(S_CFY_UD_S_RSIE);
        end;
      end;

    S_CFY_UD_S_RSIE: { 1 }
      Begin
        if chkCFY_UD_I_TRD.Checked then
        begin
          GoToState(S_CFY_UD_S_SDIC);
        end
        else if chkCFY_UD_I_FSRD.Checked then
        begin
          GoToState(S_CFY_UD_S_FDIC);
        end;
      end;

    S_CFY_UD_S_SDIC: { 2 }
      Begin
        if chkCFY_UD_I_STA.Checked then
        begin
          GoToState(S_CFY_UD_S_SAIE);
        end;
      end;

    S_CFY_UD_S_SAIE: { 3 }
      Begin
        if chkCFY_UD_I_ANS.Checked then
        begin
          GoToState(S_CFY_UD_S_RSIE);
        end;
      end;

    S_CFY_UD_S_FDIC: { 4 }
      Begin
        if chkCFY_UD_I_FRS.Checked then
        begin
          GoToState(S_CFY_UD_S_FRSE);
        end;
      end;

    S_CFY_UD_S_FRSE: { 5 }
      Begin
        if chkCFY_UD_I_FTA.Checked then
        begin
          GoToState(S_CFY_UD_S_FAIL);
        end;
      end;

    S_CFY_UD_S_FAIL: { 6 }
      Begin
        if chkCFY_UD_I_ANS.Checked then
        begin
          GoToState(S_CFY_UD_S_RSIE);
        end;
      end;

  else { illegal }
    begin
      Showmessage('Illegal State');
      GoToState(S_CFY_UD_S_INIT);
    end;
  end;

  // simulate edge sensitivity by turning things off
  chkCFY_UD_I_TRD.Checked := false;
  chkCFY_UD_I_FSRD.Checked := false;
end;

procedure TfrmCFY_UD.InputClick(Sender: TObject);
begin
  if chkAuto.Checked then
  begin
    ProcessTransitions;
  end;
end;

procedure TfrmCFY_UD.cmbStateChange(Sender: TObject);
begin
  SetState(cmbState.ItemIndex);
end;

procedure TfrmCFY_UD.GoToState(iState: integer);
begin
  cmbState.ItemIndex := iState;
  SetState(cmbState.ItemIndex);
end;

procedure TfrmCFY_UD.SetState(iState: integer);
begin
  case iState of
    S_CFY_UD_S_INIT:
      Begin
        chkCFY_UD_O_TRD.Checked := false;
        chkCFY_UD_O_TA.Checked := false;
        chkCFY_UD_O_ANS.Checked := false;
        chkCFY_UD_O_FSRD.Checked := false;
        chkCFY_UD_O_FRS.Checked := false;
        chkCFY_UD_O_UFA.Checked := false;

        chkCFY_UD_O_ERM_STRD.Checked := false;
        chkCFY_UD_O_ERM_FSRD.Checked := false;
        chkCFY_UD_O_LFY_FSRD.Checked := false;
      end;

    S_CFY_UD_S_RSIE:
      Begin
        chkCFY_UD_O_TRD.Checked := false;
        chkCFY_UD_O_TA.Checked := false;
        chkCFY_UD_O_ANS.Checked := true;
        chkCFY_UD_O_FSRD.Checked := false;
        chkCFY_UD_O_FRS.Checked := false;
        chkCFY_UD_O_UFA.Checked := false;

        chkCFY_UD_O_ERM_STRD.Checked := true;
        chkCFY_UD_O_ERM_FSRD.Checked := false;
        chkCFY_UD_O_LFY_FSRD.Checked := false;
      end;

    S_CFY_UD_S_SDIC:
      Begin
        chkCFY_UD_O_TRD.Checked := true;
        chkCFY_UD_O_TA.Checked := false;
        chkCFY_UD_O_ANS.Checked := false;
        chkCFY_UD_O_FSRD.Checked := false;
        chkCFY_UD_O_FRS.Checked := false;
        chkCFY_UD_O_UFA.Checked := false;

        chkCFY_UD_O_ERM_STRD.Checked := false;
        chkCFY_UD_O_ERM_FSRD.Checked := false;
        chkCFY_UD_O_LFY_FSRD.Checked := false;
      end;

    S_CFY_UD_S_SAIE:
      Begin
        chkCFY_UD_O_TRD.Checked := false;
        chkCFY_UD_O_TA.Checked := true;
        chkCFY_UD_O_ANS.Checked := false;
        chkCFY_UD_O_FSRD.Checked := false;
        chkCFY_UD_O_FRS.Checked := false;
        chkCFY_UD_O_UFA.Checked := false;

        chkCFY_UD_O_ERM_STRD.Checked := false;
        chkCFY_UD_O_ERM_FSRD.Checked := false;
        chkCFY_UD_O_LFY_FSRD.Checked := false;
      end;

    S_CFY_UD_S_FDIC:
      Begin
        chkCFY_UD_O_TRD.Checked := false;
        chkCFY_UD_O_TA.Checked := false;
        chkCFY_UD_O_ANS.Checked := false;
        chkCFY_UD_O_FSRD.Checked := true;
        chkCFY_UD_O_FRS.Checked := false;
        chkCFY_UD_O_UFA.Checked := false;

        chkCFY_UD_O_ERM_STRD.Checked := false;
        chkCFY_UD_O_ERM_FSRD.Checked := false;
        chkCFY_UD_O_LFY_FSRD.Checked := false;
      end;

    S_CFY_UD_S_FRSE:
      Begin
        chkCFY_UD_O_TRD.Checked := false;
        chkCFY_UD_O_TA.Checked := false;
        chkCFY_UD_O_ANS.Checked := false;
        chkCFY_UD_O_FSRD.Checked := false;
        chkCFY_UD_O_FRS.Checked := true;
        chkCFY_UD_O_UFA.Checked := false;

        chkCFY_UD_O_ERM_STRD.Checked := false;
        chkCFY_UD_O_ERM_FSRD.Checked := true;
        chkCFY_UD_O_LFY_FSRD.Checked := true;
      end;

    S_CFY_UD_S_FAIL:
      Begin
        chkCFY_UD_O_TRD.Checked := false;
        chkCFY_UD_O_TA.Checked := false;
        chkCFY_UD_O_ANS.Checked := false;
        chkCFY_UD_O_FSRD.Checked := false;
        chkCFY_UD_O_FRS.Checked := false;
        chkCFY_UD_O_UFA.Checked := true;

        chkCFY_UD_O_ERM_STRD.Checked := false;
        chkCFY_UD_O_ERM_FSRD.Checked := false;
        chkCFY_UD_O_LFY_FSRD.Checked := false;
      end;

  else
    begin
      Showmessage('Illegal State');
    end;
  end;

  // pass on the output states
  frmERM_UA.chkERM_UA_I_TWA.Checked := chkCFY_UD_O_ERM_STRD.Checked;
  frmERM_UA.chkERM_UA_I_UFRD.Checked := chkCFY_UD_O_ERM_FSRD.Checked;
  frmLFY_UA.chkLFY_UA_I_FSRD.Checked := chkCFY_UD_O_LFY_FSRD.Checked;
  //frmLFY_UA.chkLFY_UA_I_FRSD.Checked := chkCFY_UD_O_LFY_FSRD.Checked;
end;

ERM_UA Panel

Code:

const
  S_ERM_UA_S_INIT = 0;
  S_ERM_UA_S_RSIE = 1;
  S_ERM_UA_S_SDIC = 2;
  S_ERM_UA_S_SAIE = 3;
  S_ERM_UA_S_FDIC = 4;
  S_ERM_UA_S_FRSE = 5;
  S_ERM_UA_S_FAIL = 6;

implementation

{$R *.dfm}

uses
  fCFY_UD,
  fERM_UD,
  fLFY_UA;

procedure TfrmERM_UA.btnStepClick(Sender: TObject);
begin
  ProcessTransitions;
end;

procedure TfrmERM_UA.ProcessTransitions;
var
  iState: integer;
begin
  iState := cmbState.ItemIndex; // get the current state

  // no see if we can transition to another state
  case iState of
    S_ERM_UA_S_INIT: { 0 }
      Begin
        if chkERM_UA_I_RNS.Checked then
        begin
          GoToState(S_ERM_UA_S_RSIE);
        end;
      end;

    S_ERM_UA_S_RSIE: { 1 }
      Begin
        if chkERM_UA_I_TWA.Checked then
        begin
          GoToState(S_ERM_UA_S_SDIC);
        end
        else if chkERM_UA_I_UFRD.Checked then
        begin
          GoToState(S_ERM_UA_S_FDIC);
        end;
      end;

    S_ERM_UA_S_SDIC: { 2 }
      Begin
        if chkERM_UA_I_AUT.Checked then
        begin
          GoToState(S_ERM_UA_S_SAIE);
        end;
      end;

    S_ERM_UA_S_SAIE: { 3 }
      Begin
        if chkERM_UA_I_RNS.Checked then
        begin
          GoToState(S_ERM_UA_S_RSIE);
        end;
      end;

    S_ERM_UA_S_FDIC: { 4 }
      Begin
        if chkERM_UA_I_FRS.Checked then
        begin
          GoToState(S_ERM_UA_S_FRSE);
        end;
      end;

    S_ERM_UA_S_FRSE: { 5 }
      Begin
        if chkERM_UA_I_UFN.Checked then
        begin
          GoToState(S_ERM_UA_S_FAIL);
        end;
      end;

    S_ERM_UA_S_FAIL: { 6 }
      Begin
        if chkERM_UA_I_RNS.Checked then
        begin
          GoToState(S_ERM_UA_S_RSIE);
        end;
      end;

  else { illegal }
    begin
      Showmessage('Illegal State');
      GoToState(S_ERM_UA_S_INIT);
    end;
  end;

  // simulate edge sensitivity by turning things off
  chkERM_UA_I_AUT.Checked := false;
  chkERM_UA_I_RNS.Checked := false;
  chkERM_UA_I_RS.Checked := false;
  chkERM_UA_I_FRS.Checked := false;
end;

procedure TfrmERM_UA.InputClick(Sender: TObject);
begin
  if chkAuto.Checked then
  begin
    ProcessTransitions;
  end;
end;

procedure TfrmERM_UA.cmbStateChange(Sender: TObject);
begin
  SetState(cmbState.ItemIndex);
end;

procedure TfrmERM_UA.GoToState(iState: integer);
begin
  cmbState.ItemIndex := iState;
  SetState(cmbState.ItemIndex);
end;

procedure TfrmERM_UA.SetState(iState: integer);
begin
  case iState of
    S_ERM_UA_S_INIT:
      Begin
        chkERM_UA_O_TWA.Checked := false;
        chkERM_UA_O_AUT.Checked := false;
        chkERM_UA_O_RNS.Checked := false;
        chkERM_UA_O_UFRD.Checked := false;
        chkERM_UA_O_FRS.Checked := false;
        chkERM_UA_O_UFN.Checked := false;

        chkERM_UA_O_CFY_SUTA.Checked := false;
        chkERM_UA_O_CFY_RNS.Checked := false;
        chkERM_UA_O_LFY_FRS.Checked := false;
        chkERM_UA_O_CFY_FRS.Checked := false;
      end;

    S_ERM_UA_S_RSIE:
      Begin
        chkERM_UA_O_TWA.Checked := false;
        chkERM_UA_O_AUT.Checked := false;
        chkERM_UA_O_RNS.Checked := true;
        chkERM_UA_O_UFRD.Checked := false;
        chkERM_UA_O_FRS.Checked := false;
        chkERM_UA_O_UFN.Checked := false;

        chkERM_UA_O_CFY_SUTA.Checked := false;
        chkERM_UA_O_CFY_RNS.Checked := true;
        chkERM_UA_O_LFY_FRS.Checked := false;
        chkERM_UA_O_CFY_FRS.Checked := false;
      end;

    S_ERM_UA_S_SDIC:
      Begin
        chkERM_UA_O_TWA.Checked := true;
        chkERM_UA_O_AUT.Checked := false;
        chkERM_UA_O_RNS.Checked := false;
        chkERM_UA_O_UFRD.Checked := false;
        chkERM_UA_O_FRS.Checked := false;
        chkERM_UA_O_UFN.Checked := false;

        chkERM_UA_O_CFY_SUTA.Checked := false;
        chkERM_UA_O_CFY_RNS.Checked := false;
        chkERM_UA_O_LFY_FRS.Checked := false;
        chkERM_UA_O_CFY_FRS.Checked := false;
      end;

    S_ERM_UA_S_SAIE:
      Begin
        chkERM_UA_O_TWA.Checked := false;
        chkERM_UA_O_AUT.Checked := true;
        chkERM_UA_O_RNS.Checked := false;
        chkERM_UA_O_UFRD.Checked := false;
        chkERM_UA_O_FRS.Checked := false;
        chkERM_UA_O_UFN.Checked := false;

        chkERM_UA_O_CFY_SUTA.Checked := false;
        chkERM_UA_O_CFY_RNS.Checked := false;
        chkERM_UA_O_LFY_FRS.Checked := false;
        chkERM_UA_O_CFY_FRS.Checked := false;
      end;

    S_ERM_UA_S_FDIC:
      Begin
        chkERM_UA_O_TWA.Checked := false;
        chkERM_UA_O_AUT.Checked := false;
        chkERM_UA_O_RNS.Checked := false;
        chkERM_UA_O_UFRD.Checked := true;
        chkERM_UA_O_FRS.Checked := false;
        chkERM_UA_O_UFN.Checked := false;

        chkERM_UA_O_CFY_SUTA.Checked := false;
        chkERM_UA_O_CFY_RNS.Checked := false;
        chkERM_UA_O_LFY_FRS.Checked := false;
        chkERM_UA_O_CFY_FRS.Checked := false;
      end;

    S_ERM_UA_S_FRSE:
      Begin
        chkERM_UA_O_TWA.Checked := false;
        chkERM_UA_O_AUT.Checked := false;
        chkERM_UA_O_RNS.Checked := false;
        chkERM_UA_O_UFRD.Checked := false;
        chkERM_UA_O_FRS.Checked := true;
        chkERM_UA_O_UFN.Checked := false;

        chkERM_UA_O_CFY_SUTA.Checked := false;
        chkERM_UA_O_CFY_RNS.Checked := false;
        chkERM_UA_O_LFY_FRS.Checked := true;
        chkERM_UA_O_CFY_FRS.Checked := true;
      end;

    S_ERM_UA_S_FAIL:
      Begin
        chkERM_UA_O_TWA.Checked := false;
        chkERM_UA_O_AUT.Checked := false;
        chkERM_UA_O_RNS.Checked := false;
        chkERM_UA_O_UFRD.Checked := false;
        chkERM_UA_O_FRS.Checked := false;
        chkERM_UA_O_UFN.Checked := true;

        chkERM_UA_O_CFY_SUTA.Checked := false;
        chkERM_UA_O_CFY_RNS.Checked := false;
        chkERM_UA_O_LFY_FRS.Checked := false;
        chkERM_UA_O_CFY_FRS.Checked := false;
      end;

  else
    begin
      Showmessage('Illegal State');
    end;
  end;

  // pass on the output states
  frmCFY_UD.chkCFY_UD_I_STA.Checked := chkERM_UA_O_CFY_SUTA.Checked;
  frmCFY_UD.chkCFY_UD_I_ANS.Checked := chkERM_UA_O_CFY_RNS.Checked;
  frmLFY_UA.chkLFY_UA_I_FRS.Checked := chkERM_UA_O_CFY_FRS.Checked;
  frmCFY_UD.chkCFY_UD_I_FRS.Checked := chkERM_UA_O_CFY_FRS.Checked;
end;

ERM_UD Panle

Code:

const
  S_ERM_UD_S_INIT = 0;
  S_ERM_UD_S_RSIL = 1;
  S_ERM_UD_S_SDIE = 2;
  S_ERM_UD_S_SAIL = 3;

implementation

{$R *.dfm}

uses
  fCFY_UD,
  fERM_UA,
  fLFY_UA;

procedure TfrmERM_UD.btnStepClick(Sender: TObject);
begin
  ProcessTransitions;
end;

procedure TfrmERM_UD.ProcessTransitions;
var
  iState: integer;
begin
  iState := cmbState.ItemIndex; // get the current state

  // no see if we can transition to another state
  case iState of
    S_ERM_UD_S_INIT: { 0 }
      Begin
        if chkERM_UD_I_ANS.Checked then
        begin
          GoToState(S_ERM_UD_S_RSIL);
        end;
      end;

    S_ERM_UD_S_RSIL: { 1 }
      Begin
        if chkERM_UD_I_TRD.Checked then
        begin
          GoToState(S_ERM_UD_S_SDIE);
        end;
      end;

    S_ERM_UD_S_SDIE: { 2 }
      Begin
        if chkERM_UD_I_UTA.Checked then
        begin
          GoToState(S_ERM_UD_S_SAIL);
        end;
      end;

    S_ERM_UD_S_SAIL: { 3 }
      Begin
        if chkERM_UD_I_ANS.Checked then
        begin
          GoToState(S_ERM_UD_S_INIT);
        end;
      end;

  else { illegal }
    begin
      Showmessage('Illegal State');
      GoToState(S_ERM_UD_S_INIT);
    end;
  end;

  // simulate edge sensitivity by turning things off
  chkERM_UD_I_TRD.Checked := false;
end;

procedure TfrmERM_UD.InputClick(Sender: TObject);
begin
  if chkAuto.Checked then
  begin
    ProcessTransitions;
  end;
end;

procedure TfrmERM_UD.cmbStateChange(Sender: TObject);
begin
  SetState(cmbState.ItemIndex);
end;

procedure TfrmERM_UD.GoToState(iState: integer);
begin
  cmbState.ItemIndex := iState;
  SetState(cmbState.ItemIndex);
end;

procedure TfrmERM_UD.SetState(iState: integer);
begin
  case iState of
    S_ERM_UD_S_INIT:
      Begin
        chkERM_UD_O_TRD.Checked := false;
        chkERM_UD_O_TA.Checked := false;
        chkERM_UD_O_ANS.Checked := false;

        chkERM_UD_O_LFY_STRD.Checked := false;
      end;

    S_ERM_UD_S_RSIL:
      Begin
        chkERM_UD_O_TRD.Checked := false;
        chkERM_UD_O_TA.Checked := false;
        chkERM_UD_O_ANS.Checked := true;

        chkERM_UD_O_LFY_STRD.Checked := true;
      end;

    S_ERM_UD_S_SDIE:
      Begin
        chkERM_UD_O_TRD.Checked := true;
        chkERM_UD_O_TA.Checked := false;
        chkERM_UD_O_ANS.Checked := false;

        chkERM_UD_O_LFY_STRD.Checked := false;
      end;

    S_ERM_UD_S_SAIL:
      Begin
        chkERM_UD_O_TRD.Checked := false;
        chkERM_UD_O_TA.Checked := true;
        chkERM_UD_O_ANS.Checked := false;

        chkERM_UD_O_LFY_STRD.Checked := false;
      end;

  else
    begin
      Showmessage('Illegal State');
    end;
  end;

  // pass on the output states
  frmLFY_UA.chkLFY_UA_I_STRD.checked := chkERM_UD_O_LFY_STRD.Checked;
end;

LFY_UA panel

Code:

const
  S_LFY_UA_S_INIT = 0;
  S_LFY_UA_S_RSIL = 1;
  S_LFY_UA_S_SDIE = 2;
  S_LFY_UA_S_SAIL = 3;
  S_LFY_UA_S_FDIC = 4;
  S_LFY_UA_S_FRSE = 5;
  S_LFY_UA_S_FAIL = 6;

implementation

{$R *.dfm}

uses
  fCFY_UD,
  fERM_UA,
  fERM_UD;

procedure TfrmLFY_UA.btnStepClick(Sender: TObject);
begin
  ProcessTransitions;
end;

procedure TfrmLFY_UA.ProcessTransitions;
var
  iState: integer;
begin
  iState := cmbState.ItemIndex; // get the current state

  // no see if we can transition to another state
  case iState of
    S_LFY_UA_S_INIT: { 0 }
      Begin
        if chkLFY_UA_I_RNS.Checked then
        begin
          GoToState(S_LFY_UA_S_RSIL);
        end;
      end;

    S_LFY_UA_S_RSIL: { 1 }
      Begin
        if chkLFY_UA_I_STRD.Checked then
        begin
          GoToState(S_LFY_UA_S_SDIE);
        end
        else if chkLFY_UA_I_FSRD.Checked then
        begin
          GoToState(S_LFY_UA_S_FDIC);
        end;
      end;

    S_LFY_UA_S_SDIE: { 2 }
      Begin
        if chkLFY_UA_I_UTA.Checked then
        begin
          GoToState(S_LFY_UA_S_SAIL);
        end;
      end;

    S_LFY_UA_S_SAIL: { 3 }
      Begin
        if chkLFY_UA_I_RNS.Checked then
        begin
          GoToState(S_LFY_UA_S_RSIL);
        end;
      end;

    S_LFY_UA_S_FDIC: { 4 }
      Begin
        if chkLFY_UA_I_FRS.Checked then
        begin
          GoToState(S_LFY_UA_S_FRSE);
        end;
      end;

    S_LFY_UA_S_FRSE: { 5 }
      Begin
        if chkLFY_UA_I_UFA.Checked then
        begin
          GoToState(S_LFY_UA_S_FAIL);
        end;
      end;

    S_LFY_UA_S_FAIL: { 6 }
      Begin
        if chkLFY_UA_I_RNS.Checked then
        begin
          GoToState(S_LFY_UA_S_RSIL);
        end;
      end;

  else { illegal }
    begin
      Showmessage('Illegal State');
      GoToState(S_LFY_UA_S_INIT);
    end;
  end;

  // simulate edge sensitivity by turning things off
  chkLFY_UA_I_UTA.Checked := false;
  chkLFY_UA_I_RNS.Checked := false;
  chkLFY_UA_I_UFA.Checked := false;
end;

procedure TfrmLFY_UA.InputClick(Sender: TObject);
begin
  if chkAuto.Checked then
  begin
    ProcessTransitions;
  end;
end;

procedure TfrmLFY_UA.cmbStateChange(Sender: TObject);
begin
  SetState(cmbState.ItemIndex);
end;

procedure TfrmLFY_UA.GoToState(iState: integer);
begin
  cmbState.ItemIndex := iState;
  SetState(cmbState.ItemIndex);
end;

procedure TfrmLFY_UA.SetState(iState: integer);
begin
  case iState of
    S_LFY_UA_S_INIT:
      Begin
        chkLFY_UA_O_TWA.Checked := false;
        chkLFY_UA_O_UTA.Checked := false;
        chkLFY_UA_O_RNS.Checked := false;
        chkLFY_UA_O_UFRD.Checked := false;
        chkLFY_UA_O_FRS.Checked := false;
        chkLFY_UA_O_UFA.Checked := false;

        chkLFY_UA_O_ERM_SUTA.Checked := false;
        chkLFY_UA_O_ERM_RNS.Checked := false;
        chkLFY_UA_O_CFY_UFA.Checked := false;
        chkLFY_UA_O_ERM_UFA.Checked := false;
      end;

    S_LFY_UA_S_RSIL:
      Begin
        chkLFY_UA_O_TWA.Checked := false;
        chkLFY_UA_O_UTA.Checked := false;
        chkLFY_UA_O_RNS.Checked := true;
        chkLFY_UA_O_UFRD.Checked := false;
        chkLFY_UA_O_FRS.Checked := false;
        chkLFY_UA_O_UFA.Checked := false;

        chkLFY_UA_O_ERM_SUTA.Checked := false;
        chkLFY_UA_O_ERM_RNS.Checked := true;
        chkLFY_UA_O_CFY_UFA.Checked := false;
        chkLFY_UA_O_ERM_UFA.Checked := false;
      end;

    S_LFY_UA_S_SDIE:
      Begin
        chkLFY_UA_O_TWA.Checked := true;
        chkLFY_UA_O_UTA.Checked := false;
        chkLFY_UA_O_RNS.Checked := false;
        chkLFY_UA_O_UFRD.Checked := false;
        chkLFY_UA_O_FRS.Checked := false;
        chkLFY_UA_O_UFA.Checked := false;

        chkLFY_UA_O_ERM_SUTA.Checked := false;
        chkLFY_UA_O_ERM_RNS.Checked := false;
        chkLFY_UA_O_CFY_UFA.Checked := false;
        chkLFY_UA_O_ERM_UFA.Checked := false;
      end;

    S_LFY_UA_S_SAIL:
      Begin
        chkLFY_UA_O_TWA.Checked := false;
        chkLFY_UA_O_UTA.Checked := true;
        chkLFY_UA_O_RNS.Checked := false;
        chkLFY_UA_O_UFRD.Checked := false;
        chkLFY_UA_O_FRS.Checked := false;
        chkLFY_UA_O_UFA.Checked := false;

        chkLFY_UA_O_ERM_SUTA.Checked := true;
        chkLFY_UA_O_ERM_RNS.Checked := false;
        chkLFY_UA_O_CFY_UFA.Checked := false;
        chkLFY_UA_O_ERM_UFA.Checked := false;
      end;

    S_LFY_UA_S_FDIC:
      Begin
        chkLFY_UA_O_TWA.Checked := false;
        chkLFY_UA_O_UTA.Checked := false;
        chkLFY_UA_O_RNS.Checked := false;
        chkLFY_UA_O_UFRD.Checked := true;
        chkLFY_UA_O_FRS.Checked := false;
        chkLFY_UA_O_UFA.Checked := false;

        chkLFY_UA_O_ERM_SUTA.Checked := false;
        chkLFY_UA_O_ERM_RNS.Checked := false;
        chkLFY_UA_O_CFY_UFA.Checked := false;
        chkLFY_UA_O_ERM_UFA.Checked := false;
      end;

    S_LFY_UA_S_FRSE:
      Begin
        chkLFY_UA_O_TWA.Checked := false;
        chkLFY_UA_O_UTA.Checked := false;
        chkLFY_UA_O_RNS.Checked := false;
        chkLFY_UA_O_UFRD.Checked := true;
        chkLFY_UA_O_FRS.Checked := true;
        chkLFY_UA_O_UFA.Checked := false;

        chkLFY_UA_O_ERM_SUTA.Checked := false;
        chkLFY_UA_O_ERM_RNS.Checked := false;
        chkLFY_UA_O_CFY_UFA.Checked := false;
        chkLFY_UA_O_ERM_UFA.Checked := false;
      end;

    S_LFY_UA_S_FAIL:
      Begin
        chkLFY_UA_O_TWA.Checked := false;
        chkLFY_UA_O_UTA.Checked := false;
        chkLFY_UA_O_RNS.Checked := false;
        chkLFY_UA_O_UFRD.Checked := false;
        chkLFY_UA_O_FRS.Checked := false;
        chkLFY_UA_O_UFA.Checked := true;

        chkLFY_UA_O_ERM_SUTA.Checked := false;
        chkLFY_UA_O_ERM_RNS.Checked := false;
        chkLFY_UA_O_CFY_UFA.Checked := true;
        chkLFY_UA_O_ERM_UFA.Checked := true;
      end;

  else
    begin
      Showmessage('Illegal State');
    end;
  end;

  // pass on the output states
  frmERM_UD.chkERM_UD_I_UTA.Checked := chkLFY_UA_O_ERM_SUTA.Checked;
  frmERM_UD.chkERM_UD_I_ANS.Checked := chkLFY_UA_O_ERM_RNS.Checked;
  frmCFY_UD.chkCFY_UD_I_FTA.Checked := chkLFY_UA_O_CFY_UFA.Checked;
  frmERM_UA.chkERM_UA_I_FRS.Checked := chkLFY_UA_O_ERM_UFA.Checked;
end;

I've run some basic tests and it *seems* to operate as far as I can see.

You will have to go throug a series of tests, and if you have skype it may be worth me talking you through it.

(*steve*) · Nov 11, 2013

I really should comment my code more... I wasn't intending on showing it off when I wrote it...

(*steve*) · Nov 11, 2013

And for the curious, when running it looks like this:

P4 Modeller · Nov 11, 2013

Hi Steve

In doing so, I found a few errors in your states and transitions, mostly small and easily fixed. In general they fell into one of 3 categories:

1) Mentioning the wrong panel
2) Typo or alternate spellings of signals, inputs, outputs, etc.
3) lack of setting output signals.

Now I'm embarresed

WOW didnt expect the rest of the posts ThankYou

(*steve*) · Nov 11, 2013

I have sent P4 Modeller a copy of the executable which models part of his setup.

Here is the email (which might be of interest to others)

Here is a copy of the executable (sans the executable).

When you run it, press the start button and 4 other windows will open.

Each window is one of your panels and labelled as such.

There are 4 panes on each panel. Input controls, input signals, output indications, output signals, and control stuff.

Input Controls:

These are the buttons on your panel. Clicking on these are like pressing the button. You'll not see this checked (unless automatic is unchecked). These are all treated as "edge sensitive" by turning them off as soon as the state machine inspects them.

Input Signals:

These are the signals that come from other places. The linkage is shown. These will appear as checked if their source is checked.

You can click on these to override them, but I'd advise you not to.

Output Indications:

These are the lights and such. They are checked when on, unchecked when off. I don't show flashing.

You can't click on them.

Output Signals:

These are the signals sent to other panels. They are checked when asserted, and unchecked when not asserted. You can't click on them.

Control stuff:

At the bottom of each panel is a dropdown showing the current state. If you wish to, you can set a state by manually changing this (this is not something you need to do often - or preferably at all). This will update automatically as the state machine operates.

The Step button allows you to manually run the state machine to set the new state from the current state and the input controls and signals.

The Automatic checkbox allows the state machine to automatically run each time a state changes (essentially it runs continually). If you turn this off, the inputs can change (and you'll see the input controls checked if you click on them) but the state machine won't interpret them until you press the step button. This may be useful in looking carefully at what the initial and final states are if something goes awry.

Note that I have had to determine when the output signals should be asserted, and I've done that from my limited understanding of your setup.

The first thing you should do is turn all the panels to manual and go through each state. Make sure I have set the correct output indications and signals. You will also be able to check that they link up correctly to the input signals on other panels.

One major change is that on the ERM-UA panel, you defined 3 input controls, but used 4. I figured that ERM_UA_RS might be ERM_UA_FRS but there were some indications it *might* be something different. I took the conservative approach and just added another input control.

I also assumed that the input/output signals were internally complete, that is, all of the output signals defined here are connected to input signals defined here. This meant I had to change the linkages or names slightly to do that. I think these were simply typos.

Have a go at this and see what you think.

Of course, it goes without saying that you should run your virus scanner over this code before you run it.

Steve

p.s. I'll post these instructions in the thread as well.

P4 Modeller · Nov 12, 2013

Hi Steve,

Only had a short time this morning to look at your post

Lets hope i can get round this later

Thanks again

Mark

P4 Modeller · Nov 13, 2013

Hi Steve,

Managed to open the .EXE file

Looks very Impressive in its own right.
Have Turned them all to manual and gone through each state

The results weren't what i was expecting

Though this may be down to operator error.....ie ME

So You have chosen the UP Line Movements and you may remember that these were essentially the same as the DOWN Line Movements (LFY_DD [London Fiddle Yard _ Down Dispatch] becomes CFY_UD [Country Fiddle Yard_UP Dispatch] and ERM_DA [Eridge Main-Down Accept] becomes ERM_UA [ Eridge Main UP Dispatch]

SO the below would represent
SLOW TRAIN MOVEMENTS CFY_UA to ERM_UA if substitiuted.

SLOW TRAIN MOVEMENT LFY_DD to ERM_DA

Code:

SLOW TRAIN MOVEMENT [LFY_DD] TO [ERM_DA]

1. On ERM_DA PANEL – Next Service

Start of the sequence [ERM_DA] Panel will have [ERM_DA_O_RNS] “Ready Next Service” On.
This will have been initiated from the end of a routine by pressing [ERM_DA_I_RNS]. (discussed in Step 4).

On LFY_DD PANEL- Next Service

Start of the sequence will have [LFY_DD_O_ANS] “Awaiting Next Service” On (Flashing).
This input has come by receiving a signal from [ERM_DA_O_LFY_RNS] at [LFY_DD_I_ANS] (discussed in Step 4).

2. On LFY_DD PANEL – Dispatch

LFY Operator will (when ready) Press button [LFY_DD_I_TRD] “Train Ready Departure]
this will cause [LFY_DD_O_TRD]”Train Ready Dispatch” On and [LFY_DD_O_ANS]
“Awaiting Next Service” Off. It will also send a signal [LFY_DD_O_ERM_STRD]
back to [ERM_DA] Panel Informing Button Pressed.

On ERM_DA PANEL - Dispatch

Signal received from [LFY_DD_O_ERM_STRD] at [ERM_DA_I_TWA]. This signal will
cause [ERM_DA_O_TWA] “Train Waiting Acceptance”] On (flashing) and [ERM_DA_O_RNS] “Ready Next Service” Off.

3. On ERM_DA PANEL –Accepted

ERM Operator will (when ready) Press button [ERM_DA_I_ADT]”Accept Down Train”.
This will cause [ERM_DA_O_ ADT] “Accept Down Train” On and [ERM_DA_O_TWA]
“Train Waiting Acceptance” Off. This will also send a signal via [ERM_DA_0_LFY_SDTA] to [LFY_DD] Panel.

On LFY_DD PANEL - Accepted

Signal received from [ERM_DA_O_LFY_SDTA] at [LFY_DD_I_STA] causing [LFY_DD_O_TA]
“Train Accepted” On and [LYD_DD_O_TRD] “Train Ready Dispatch” Off.

4. On ERM_DA PANEL – End Routine

ERM Operator will control the train movement to his location. Then ERM will press
button [ERM_DA_I_RNS]. This will cause [ERM_DA_O_RNS] “Ready Next Service” On
and [ERM_DA_O_ADT] “Accept Down Train” Off. This will also send a signal [ERM_DA_O_LFY_RNS]
to the [LFY_DD] Panel (step 1)

On LFY_DD PANEL – End Routine

Signal received from [ERM_DA_O_LFY_RNS] at [LFY_DD_I_ANS] causing [LFY_DD_O_ANS]
“Awaiting Next Service” On (Flashing) and [LFY_DD_O_TA]”Train Accepted Off (step 1).

SO we start the sequence at State (Initial/Reset)

Everything on these 2 panels is off so all is good for the time being

This essentially would be the start of a running session for us so what i was expecting was for the receiving [ERM_DA (ERM_UA)] operator to express his wish to have a train movement by pressing the "Ready Next Service" button.

This is essentially

4. On ERM_DA PANEL – End Routine

ERM Operator will control the train movement to his location. Then ERM will press
button [ERM_DA_I_RNS]. This will cause [ERM_DA_O_RNS] “Ready Next Service” On
and [ERM_DA_O_ADT] “Accept Down Train” Off. This will also send a signal [ERM_DA_O_LFY_RNS]
to the [LFY_DD] Panel (step 1)

On LFY_DD PANEL – End Routine

Signal received from [ERM_DA_O_LFY_RNS] at [LFY_DD_I_ANS] causing [LFY_DD_O_ANS]
“Awaiting Next Service” On (Flashing) and [LFY_DD_O_TA]”Train Accepted Off (step 1).

WITHOUT TURNING OFF THE TRAIN ACCEPTED FUNCTION.

So here from (INIT) State (below) i have pressed CFY_UA_I_RNS and got the results i expected on that panel (Input/Outputs/State and also on the ERM_UA panel with regards to the input signal.

And Now (below) all i have done is pressed the "STEP" button on CFY_UD Panel ( i presume this is the correct way to operate the panel).

What i was expecting to happen was for the input signal received via the CFY_UA_I_RNS to be actioned by pressing the "STEP" button.

Actually it sorta has.... the State on ERM_UA has changed to the correct one ... only problem is that Output Signal CFY_UD_O_ERM_STRD has been checked?
incidentally the Output Signal has not been changed from the Down Line to the Up line in the program... minor typo

This should only happen when the CFY Operator has pressed button CFY_UD_I_TRD as below ..Dont forget to substitute CFY_UD for LFY_DD and ERM_UA for ERM_DA

2. On LFY_DD PANEL – Dispatch

LFY Operator will (when ready) Press button [LFY_DD_I_TRD] “Train Ready Departure]
this will cause [LFY_DD_O_TRD]”Train Ready Dispatch” On and [LFY_DD_O_ANS]
“Awaiting Next Service” Off. It will also send a signal [LFY_DD_O_ERM_STRD]
back to [ERM_DA] Panel Informing Button Pressed.

On ERM_DA PANEL - Dispatch

Signal received from [LFY_DD_O_ERM_STRD] at [ERM_DA_I_TWA]. This signal will
cause [ERM_DA_O_TWA] “Train Waiting Acceptance”] On (flashing) and [ERM_DA_O_RNS] “Ready Next Service” Off.

And because that output has been checked it has impacted ERM_UA Panel

And by passed the button press[ CFY_U_I_TRD] totally

This post is ofcourse assuming that i am using the program you emailed correctly..

Mark

P4 Modeller · Nov 13, 2013

Following on from the previous post....(computer crash...grrrr)

Dont forget to substitiute
CFY_UD for LFY_DD
ERM_UA for ERM_DA

2. On LFY_DD PANEL – Dispatch

LFY Operator will (when ready) Press button [LFY_DD_I_TRD] “Train Ready Departure]
this will cause [LFY_DD_O_TRD]”Train Ready Dispatch” On and [LFY_DD_O_ANS]
“Awaiting Next Service” Off. It will also send a signal [LFY_DD_O_ERM_STRD]
back to [ERM_DA] Panel Informing Button Pressed.

On ERM_DA PANEL - Dispatch

Signal received from [LFY_DD_O_ERM_STRD] at [ERM_DA_I_TWA]. This signal will
cause [ERM_DA_O_TWA] “Train Waiting Acceptance”] On (flashing) and [ERM_DA_O_RNS] “Ready Next Service” Off.

Pressing CFY_UD_I_TRD then "STEP" should give the following results

StateCFY_UD_S_SDIC (correct)
Output Indicator CFY_UD_O_TRD ON (correct)
Input SignalCFY_UD_I_ANS OFF (incorrect)
output Signal CFY_UD_ERM_O_STRD ON (incorrect)

And This Impacts the ERM_UA Panel as Now its not getting information that CFY_UD_I_TRD has been pressed and is stuck in state ERM_UA_S_RSIE.
because the output signal from CFY_UD has now been switched off.

However the state can be changed with "manual intervention" by checking the input signal ERM_UA_I_TWA and pressing "STEP" as below this sets it to state (SDIC)

BOTH CFY_UD and ERM_UA ARE NOW AT STATE (SDIC)

3. On ERM_DA PANEL –Accepted

ERM Operator will (when ready) Press button [ERM_DA_I_ADT]”Accept Down Train”.
This will cause [ERM_DA_O_ ADT] “Accept Down Train” On and [ERM_DA_O_TWA]
“Train Waiting Acceptance” Off. This will also send a signal via [ERM_DA_0_LFY_SDTA] to [LFY_DD] Panel.

On LFY_DD PANEL - Accepted

Signal received from [ERM_DA_O_LFY_SDTA] at [LFY_DD_I_STA] causing [LFY_DD_O_TA]
“Train Accepted” On and [LYD_DD_O_TRD] “Train Ready Dispatch” Off.

So Now i have checked ERM_UA_I_AUT on the ERM_UA Panel to simulate a button press (i have also re-checked input signal ERM_UA_I_TWA which it should have recieved to get to the state its in.

If I now press "STEP" on this panel i would expect to see the following
State
Change of State from ERM_UA_S_SDIC to ERM_UA_S_SUTA

Input Controls
ERM_UA_I_AUT Checked

Output Indicators
ERM_UA_O_TWA go from checked to unchecked (OFF)
ERM_UA_O_AUT go to checked (ON)

Input Signals

ERM_UA_I_TWA go from checked to unchecked

Output Signals

ERM_UA_O_CFY_SUTA go to checked

State Change (correct)
output Indicators (correct)
Input Signal (incorrect)
Output Signal (incorrect)

Of course no output signal means CFY_UA will not change state

Mark
Just wish i could help more
understand the principles, cant write them into code ...

PS BTW

One major change is that on the ERM-UA panel, you defined 3 input controls, but used 4. I figured that ERM_UA_RS might be ERM_UA_FRS but there were some indications it *might* be something different. I took the conservative approach and just added another input control.

Yes they are the same... RS = Route Set, FRS = Fast Route Set.... it was changed to the latter as it only comes into operation on a "Fast Train Movement" so it made more sense to call it FRS

(*steve*) · Nov 13, 2013

I'll have to get onto this again tonight.

I think I used your set of transitions from post 149

I didn't have time to go through your walk-throughs after writing it or I may have noticed I had done the other line!

It does sound like you're using the software correctly, Although you really need to hit step on every panel (and possibly keep pressing them until nothing else changes if you want to be certain of the final result of some input).

What you can do is verify I have all the states defined correctly in terms of their outputs. Especially important is the definition of the output signals.

Start from the initial condition where everything is in reset and use the drop down list to confirm that the states produce the correct output. This is the first of three fundamental tests. If I have this wrong, then it is pointless going further.

What I'd expect is a list like this:

Foo Panel

1) When in state foo_init, the foo_o_bar_ready should be on
2) When in state foo_baring, the foo_o_bar_ready should be off
3) The output signal foo_o_widget_bar should be changed to foo_o_gadget_bar
4) The output indication bar_o_bar_mode looks like a typo, it should be foo_o_bar_mode

All other outputs are correct as currently encoded.

So I currently note that:

CFY_UD panel
1) When in state CFY_UD_S_SDIC output Signal CFY_UD_ERM_O_STRD is ON but should be OFF

What I also now know is that there is a state (or states) where that signal needs to be ON, but I don't know what they are. I hope you will lest another state where this output signal is off but should be on.

Note that it is not correct to say that an input has a correct state because an input only takes you to a state. If a change to that input should take you to another state, we need a transition which includes that. And testing the transitions is the next task

It may be helpful to look at this part of the code (which is different to what you will write on the arduino, but you should be able to see the corresponding meaning:

Code:

procedure TfrmCFY_UD.SetState(iState: integer);
begin
  case iState of
    S_CFY_UD_S_INIT:
      Begin
        chkCFY_UD_O_TRD.Checked := false;
        chkCFY_UD_O_TA.Checked := false;
        chkCFY_UD_O_ANS.Checked := false;
        chkCFY_UD_O_FSRD.Checked := false;
        chkCFY_UD_O_FRS.Checked := false;
        chkCFY_UD_O_UFA.Checked := false;

        chkCFY_UD_O_ERM_STRD.Checked := false;
        chkCFY_UD_O_ERM_FSRD.Checked := false;
        chkCFY_UD_O_LFY_FSRD.Checked := false;
      end;

    S_CFY_UD_S_RSIE:
      Begin
        chkCFY_UD_O_TRD.Checked := false;
        chkCFY_UD_O_TA.Checked := false;
        chkCFY_UD_O_ANS.Checked := true;
        chkCFY_UD_O_FSRD.Checked := false;
        chkCFY_UD_O_FRS.Checked := false;
        chkCFY_UD_O_UFA.Checked := false;

        chkCFY_UD_O_ERM_STRD.Checked := true;
        chkCFY_UD_O_ERM_FSRD.Checked := false;
        chkCFY_UD_O_LFY_FSRD.Checked := false;
      end;

    S_CFY_UD_S_SDIC:
      Begin
        chkCFY_UD_O_TRD.Checked := true;
        chkCFY_UD_O_TA.Checked := false;
        chkCFY_UD_O_ANS.Checked := false;
        chkCFY_UD_O_FSRD.Checked := false;
        chkCFY_UD_O_FRS.Checked := false;
        chkCFY_UD_O_UFA.Checked := false;

        chkCFY_UD_O_ERM_STRD.Checked := false;
        chkCFY_UD_O_ERM_FSRD.Checked := false;
        chkCFY_UD_O_LFY_FSRD.Checked := false;
      end;

    S_CFY_UD_S_SAIE:
      Begin
        chkCFY_UD_O_TRD.Checked := false;
        chkCFY_UD_O_TA.Checked := true;
        chkCFY_UD_O_ANS.Checked := false;
        chkCFY_UD_O_FSRD.Checked := false;
        chkCFY_UD_O_FRS.Checked := false;
        chkCFY_UD_O_UFA.Checked := false;

        chkCFY_UD_O_ERM_STRD.Checked := false;
        chkCFY_UD_O_ERM_FSRD.Checked := false;
        chkCFY_UD_O_LFY_FSRD.Checked := false;
      end;

    S_CFY_UD_S_FDIC:
      Begin
        chkCFY_UD_O_TRD.Checked := false;
        chkCFY_UD_O_TA.Checked := false;
        chkCFY_UD_O_ANS.Checked := false;
        chkCFY_UD_O_FSRD.Checked := true;
        chkCFY_UD_O_FRS.Checked := false;
        chkCFY_UD_O_UFA.Checked := false;

        chkCFY_UD_O_ERM_STRD.Checked := false;
        chkCFY_UD_O_ERM_FSRD.Checked := false;
        chkCFY_UD_O_LFY_FSRD.Checked := false;
      end;

    S_CFY_UD_S_FRSE:
      Begin
        chkCFY_UD_O_TRD.Checked := false;
        chkCFY_UD_O_TA.Checked := false;
        chkCFY_UD_O_ANS.Checked := false;
        chkCFY_UD_O_FSRD.Checked := false;
        chkCFY_UD_O_FRS.Checked := true;
        chkCFY_UD_O_UFA.Checked := false;

        chkCFY_UD_O_ERM_STRD.Checked := false;
        chkCFY_UD_O_ERM_FSRD.Checked := true;
        chkCFY_UD_O_LFY_FSRD.Checked := true;
      end;

    S_CFY_UD_S_FAIL:
      Begin
        chkCFY_UD_O_TRD.Checked := false;
        chkCFY_UD_O_TA.Checked := false;
        chkCFY_UD_O_ANS.Checked := false;
        chkCFY_UD_O_FSRD.Checked := false;
        chkCFY_UD_O_FRS.Checked := false;
        chkCFY_UD_O_UFA.Checked := true;

        chkCFY_UD_O_ERM_STRD.Checked := false;
        chkCFY_UD_O_ERM_FSRD.Checked := false;
        chkCFY_UD_O_LFY_FSRD.Checked := false;
      end;

  else
    begin
      Showmessage('Illegal State');
    end;
  end;

  // pass on the output states
  frmERM_UA.chkERM_UA_I_TWA.Checked := chkCFY_UD_O_ERM_STRD.Checked;
  frmERM_UA.chkERM_UA_I_UFRD.Checked := chkCFY_UD_O_ERM_FSRD.Checked;
  frmLFY_UA.chkLFY_UA_I_FSRD.Checked := chkCFY_UD_O_LFY_FSRD.Checked;
  //frmLFY_UA.chkLFY_UA_I_FRSD.Checked := chkCFY_UD_O_LFY_FSRD.Checked;
end;

All you really need to know is that this:

Code:

  case iState of

is the start of the equivalent of a switch statement. I'm looking at what to do in each state.

Code:

    S_CFY_UD_S_INIT:

This is the state we're looking for. The next block happens if iState (the state we're switching to) is equal to S_CFY_UD_S_INIT. I added the S_ at the beginning to tell me it is a state, so this state is CFY_UD_S_INIT.

Code:

      Begin
        chkCFY_UD_O_TRD.Checked := false;
        chkCFY_UD_O_TA.Checked := false;
        chkCFY_UD_O_ANS.Checked := false;
        chkCFY_UD_O_FSRD.Checked := false;
        chkCFY_UD_O_FRS.Checked := false;
        chkCFY_UD_O_UFA.Checked := false;

        chkCFY_UD_O_ERM_STRD.Checked := false;
        chkCFY_UD_O_ERM_FSRD.Checked := false;
        chkCFY_UD_O_LFY_FSRD.Checked := false;
      end;

and this is what happens in that case.

Code:

        chkCFY_UD_O_TRD.Checked := false;

The input and output signals and indications are all represented as checkboxes on the form. The prefix "chk" is standard for this. So this is the output indication CFY_UD_O_TRD.

I am determining if the box is checked or not.

A checkbox has a property "checked" that I can refer to with the name of the checkbox followed by a dot and then the keyword "checked".

The assignment operator is :=, this means the variable on the left takes the value on the right.

The value on the right is "false", which means unchecked (or OFF). You would be unlikely to be surprised that the other value is "true", representing a checked box (or ON).

Finally the statement ends in a semicolon.

So the whole line

Code:

        chkCFY_UD_O_TRD.Checked := false;

means turn the output indication CFY_UD_O_TRD off. When we are in the init state this output indication is off.

As you have seen, when you start up the program, this panel is in the init state, and this indication is unchecked.

Going through the states, you will see that I have tried to copy exactly what you have said for the output indications. I needed to figure out the output signals because they were not specified. I expect them to be wrong.

P4 Modeller · Nov 14, 2013

Panel CFY_UD

1. Input Signal CFY_UD_I_FTA typo error ERM_UA_O_CFY_UFA should read LFY_UA_O_CFY_UFA
2. Output Signal CFY_UD_O_ERM_FSRD typo error ERM_DA_I_UFRD should read ERM_UA_I_UFRD
3. Output Signal CFY_UD_O_ERM_STRD typo error ERM_DA_I_TWA should read ERM_UA_I_TWA
4. When in State CFY_UD_S_RSIE Output Signal CFY_UD_O_ERM_STRD should be false
5. When in State CFY_UD_S_SDIC Output Signal CFY_UD_O_ERM_STRD should be true
6. When in State CFY_UD_S_FDIC Output Signal CFY_UD_O_ERM_FSRD should be true
7. When in State CFY_UD_S_FDIC Output Signal CFY_UD_O_LFY_FSRD should be true
8. When in State CFY_UD_S_FRSE Output Signal CFY_UD_O_ERM_FSRD should be false
9. When in State CFY_UD_S_FRSE Output Signal CFY_UD_O_LFY_FSRD should be false

The changes made below should cover these (tongue in cheek)

0. State CFY_UD_S_INIT (Initial)

Output Indicators

CFY_UD_O_TRD = Off
CFY_UD_O_TA = Off
CFY_UD_O_ANS = Off
CFY_UD_O_FSRD= Off
CFY_UD_O_FRS = Off
CFY_UD_O_UFA = Off

Input Signals

CFY_UD_I_STA = Off
CFY_UD_I_ANS = Off
CFY_UD_I_FRS = Off
CFY_UD_I_FTA = Off

Output Signals

CFY_UD_O_ERM_STRD = Off
CFY_UD_O_ERM_FSRD = Off
CFY_UD_O_LFY_FSRD = Off

Code:

Begin
        chkCFY_UD_O_TRD.Checked := false;
        chkCFY_UD_O_TA.Checked := false;
        chkCFY_UD_O_ANS.Checked := false;
        chkCFY_UD_O_FSRD.Checked := false;
        chkCFY_UD_O_FRS.Checked := false;
        chkCFY_UD_O_UFA.Checked := false;

        chkCFY_UD_O_ERM_STRD.Checked := false;
        chkCFY_UD_O_ERM_FSRD.Checked := false;
        chkCFY_UD_O_LFY_FSRD.Checked := false;
      end;

1. State CFY_UD_S_RSIE (Ready Service next Initiated ERM)

Output Indicators

CFY_UD_O_TRD = Off
CFY_UD_O_TA = Off
CFY_UD_O_ANS = ON
CFY_UD_O_FSRD= Off
CFY_UD_O_FRS = Off
CFY_UD_O_UFA = Off

Input Signals

CFY_UD_I_STA = Off
CFY_UD_I_ANS = ON
CFY_UD_I_FRS = Off
CFY_UD_I_FTA = Off

Output Signals

CFY_UD_O_ERM_STRD = Off
CFY_UD_O_ERM_FSRD = Off
CFY_UD_O_LFY_FSRD = Off

Code:

Begin
        chkCFY_UD_O_TRD.Checked := false;
        chkCFY_UD_O_TA.Checked := false;
        chkCFY_UD_O_ANS.Checked := true;
        chkCFY_UD_O_FSRD.Checked := false;
        chkCFY_UD_O_FRS.Checked := false;
        chkCFY_UD_O_UFA.Checked := false;

        chkCFY_UD_O_ERM_STRD.Checked := false;
        chkCFY_UD_O_ERM_FSRD.Checked := false;
        chkCFY_UD_O_LFY_FSRD.Checked := false;
      end;

2. State CFY_UD_S_SDIC (Slow Dispatch ready Initiated CFY)

Output Indicators

CFY_UD_O_TRD = ON
CFY_UD_O_TA = Off
CFY_UD_O_ANS = Off
CFY_UD_O_FSRD= Off
CFY_UD_O_FRS = Off
CFY_UD_O_UFA = Off

Input Signals

CFY_UD_I_STA = Off
CFY_UD_I_ANS = Off
CFY_UD_I_FRS = Off
CFY_UD_I_FTA = Off

Output Signals

CFY_UD_O_ERM_STRD = ON (to ERM_UA Panel)
CFY_UD_O_ERM_FSRD = Off
CFY_UD_O_LFY_FSRD = Off

Code:

Begin
        chkCFY_UD_O_TRD.Checked := true;
        chkCFY_UD_O_TA.Checked := false;
        chkCFY_UD_O_ANS.Checked := false;
        chkCFY_UD_O_FSRD.Checked := false;
        chkCFY_UD_O_FRS.Checked := false;
        chkCFY_UD_O_UFA.Checked := false;

        chkCFY_UD_O_ERM_STRD.Checked := true;
        chkCFY_UD_O_ERM_FSRD.Checked := false;
        chkCFY_UD_O_LFY_FSRD.Checked := false;
      end;

3. State CFY_UD_S_SAIE (Slow Accepted Initiated ERM)

Output Indicators

CFY_UD_O_TRD = Off
CFY_UD_O_TA = ON
CFY_UD_O_ANS = Off
CFY_UD_O_FSRD= Off
CFY_UD_O_FRS = Off
CFY_UD_O_UFA = Off

Input Signals

CFY_UD_I_STA = ON
CFY_UD_I_ANS = Off
CFY_UD_I_FRS = Off
CFY_UD_I_FTA = Off

Output Signals

CFY_UD_O_ERM_STRD = Off
CFY_UD_O_ERM_FSRD = Off
CFY_UD_O_LFY_FSRD = Off

Code:

Begin
        chkCFY_UD_O_TRD.Checked := false;
        chkCFY_UD_O_TA.Checked := true;
        chkCFY_UD_O_ANS.Checked := false;
        chkCFY_UD_O_FSRD.Checked := false;
        chkCFY_UD_O_FRS.Checked := false;
        chkCFY_UD_O_UFA.Checked := false;

        chkCFY_UD_O_ERM_STRD.Checked := false;
        chkCFY_UD_O_ERM_FSRD.Checked := false;
        chkCFY_UD_O_LFY_FSRD.Checked := false;
      end;

4. State CFY_UD_S_FDIC (Fast Dispatch Initiated CFY)

Output Indicators

CFY_UD_O_TRD = Off
CFY_UD_O_TA = Off
CFY_UD_O_ANS = Off
CFY_UD_O_FSRD= ON
CFY_UD_O_FRS = Off
CFY_UD_O_UFA = Off

Input Signals

CFY_UD_I_STA = Off
CFY_UD_I_ANS = Off
CFY_UD_I_FRS = Off
CFY_UD_I_FTA = Off

Output Signals

CFY_UD_O_ERM_STRD = Off
CFY_UD_O_ERM_FSRD = ON
CFY_UD_O_LFY_FSRD = ON

Code:

Begin
        chkCFY_UD_O_TRD.Checked := false;
        chkCFY_UD_O_TA.Checked := false;
        chkCFY_UD_O_ANS.Checked := false;
        chkCFY_UD_O_FSRD.Checked := true;
        chkCFY_UD_O_FRS.Checked := false;
        chkCFY_UD_O_UFA.Checked := false;

        chkCFY_UD_O_ERM_STRD.Checked := false;
        chkCFY_UD_O_ERM_FSRD.Checked := true;
        chkCFY_UD_O_LFY_FSRD.Checked := true;
      end;

5. State CFY_UD_S_FRSE (Fast Route Set initated ERM)

Output Indicators

CFY_UD_O_TRD = Off
CFY_UD_O_TA = Off
CFY_UD_O_ANS = Off
CFY_UD_O_FSRD= Off
CFY_UD_O_FRS = ON
CFY_UD_O_UFA = Off

Input Signals

CFY_UD_I_STA = Off
CFY_UD_I_ANS = Off
CFY_UD_I_FRS = ON
CFY_UD_I_FTA = Off

Output Signals

CFY_UD_O_ERM_STRD = Off
CFY_UD_O_ERM_FSRD = Off
CFY_UD_O_LFY_FSRD = Off

Code:

Begin
        chkCFY_UD_O_TRD.Checked := false;
        chkCFY_UD_O_TA.Checked := false;
        chkCFY_UD_O_ANS.Checked := false;
        chkCFY_UD_O_FSRD.Checked := false;
        chkCFY_UD_O_FRS.Checked := true;
        chkCFY_UD_O_UFA.Checked := false;

        chkCFY_UD_O_ERM_STRD.Checked := false;
        chkCFY_UD_O_ERM_FSRD.Checked := false;
        chkCFY_UD_O_LFY_FSRD.Checked := false;
      end;

6. State CFY_UD_S_FAIL (Fast train Accepted Initated LFY)

Output Indicators

CFY_UD_O_TRD = Off
CFY_UD_O_TA = Off
CFY_UD_O_ANS = Off
CFY_UD_O_FSRD= Off
CFY_UD_O_FRS = Off
CFY_UD_O_UFA = ON

Input Signals

CFY_UD_I_STA = Off
CFY_UD_I_ANS = Off
CFY_UD_I_FRS = Off
CFY_UD_I_FTA = ON ( from LFY_UD_O_CFY_UFA..not as stated on panel)

Output Signals

CFY_UD_O_ERM_STRD = Off
CFY_UD_O_ERM_FSRD = Off
CFY_UD_O_LFY_FSRD = Off

Code:

Begin
        chkCFY_UD_O_TRD.Checked := false;
        chkCFY_UD_O_TA.Checked := false;
        chkCFY_UD_O_ANS.Checked := false;
        chkCFY_UD_O_FSRD.Checked := false;
        chkCFY_UD_O_FRS.Checked := false;
        chkCFY_UD_O_UFA.Checked := true;

        chkCFY_UD_O_ERM_STRD.Checked := false;
        chkCFY_UD_O_ERM_FSRD.Checked := false;
        chkCFY_UD_O_LFY_FSRD.Checked := false;
      end;

Valid State Transitions

State 0 CFY_UD_S_INIT
State 1 CFY_UD_S_RSIE
State 2 CFY_UD_S_SDIC
State 3 CFY_UD_S_SAIE
State 4 CFY_UD_S_FDIC
State 5 CFY_UD_S_FRSE
State 6 CFY_UD_S_FAIL

State 0 --> State 1 Trigger Input Signal CFY_UD_I_ANS = ON
State 1 --> State 2 Trigger Button Press CFY_UD_I_TRD
State 2 --> State 3 Trigger Input Signal CFY_UD_I_STA = ON
State 3 --> State 1 Trigger Input Signal CFY_UD_I_ANS = ON

State 1 --> State 4 Trigger Button Press CFY_UD_I_FRSD
State 4 --> State 5 Trigger Input Signal CFY_UD_I_FRS = ON
State 5 --> State 6 Trigger Input Signal CFY_UD_I_FTA = ON
State 6 --> State 1 Trigger Input Signal CFY_UD_I_ANS = ON

P4 Modeller · Nov 14, 2013

Panel ERM_UA

INPUT CONTROL ERM_UA_I-RS = INVALID REPLACED BY ERM_UA_I_FRS

0. State ERM_UA_S_INIT (Initial)

Output Indicators

ERM_UA_O_TWA = Off
ERM_UA_O_AUT = Off
ERM_UA_O_RNS = Off
ERM_UA_O_UFRD= Off
ERM_UA_O_FRS = Off
ERM_UA_O_UFN = Off

Input Signals

ERM_UA_I_TWA = Off
ERM_UA_I_UFRD = Off
ERM_UA_I_UFN = Off

Output Signals

ERM_UA_O_CFY_SUTA = Off
ERM_UA_O_CFY_RNS = Off
ERM_UA_O_LFY_FRS = Off
ERM_UA_O_CFY_FRS = Off

Code:

Begin
        chkERM_UA_O_TWA.Checked := false;
        chkERM_UA_O_AUT.Checked := false;
        chkERM_UA_O_RNS.Checked := false;
        chkERM_UA_O_UFRD.Checked := false;
        chkERM_UA_O_FRS.Checked := false;
        chkERM_UA_O_UFN.Checked := false;

        chkERM_UA_O_CFY_SUTA.Checked := false;
        chkERM_UA_O_CFY_RNS.Checked := false;
        chkERM_UA_O_LFY_FRS.Checked := false;
        chkERM_UA_O_CFY_FRS.Checked := false;
      end;

1. State ERM_UA_S_RSIE (Ready Service next Initiated ERM)

Output Indicators

ERM_UA_O_TWA = Off
ERM_UA_O_AUT = Off
ERM_UA_O_RNS = ON
ERM_UA_O_UFRD= Off
ERM_UA_O_FRS = Off
ERM_UA_O_UFN = Off

Input Signals

ERM_UA_I_TWA = Off
ERM_UA_I_UFRD = Off
ERM_UA_I_UFN = Off

Output Signals

ERM_UA_O_CFY_SUTA = Off
ERM_UA_O_CFY_RNS = ON
ERM_UA_O_LFY_FRS = Off
ERM_UA_O_CFY_FRS = Off

Code:

Begin
        chkERM_UA_O_TWA.Checked := false;
        chkERM_UA_O_AUT.Checked := false;
        chkERM_UA_O_RNS.Checked := true;
        chkERM_UA_O_UFRD.Checked := false;
        chkERM_UA_O_FRS.Checked := false;
        chkERM_UA_O_UFN.Checked := false;

        chkERM_UA_O_CFY_SUTA.Checked := false;
        chkERM_UA_O_CFY_RNS.Checked := true;
        chkERM_UA_O_LFY_FRS.Checked := false;
        chkERM_UA_O_CFY_FRS.Checked := false;
      end;

2. State ERM_UA_S_SDIC (Slow Dispatch ready Initiated CFY)

Output Indicators

ERM_UA_O_TWA = ON
ERM_UA_O_AUT = Off
ERM_UA_O_RNS = Off
ERM_UA_O_UFRD= Off
ERM_UA_O_FRS = Off
ERM_UA_O_UFN = Off

Input Signals

ERM_UA_I_TWA = ON
ERM_UA_I_UFRD = Off
ERM_UA_I_UFN = Off

Output Signals

ERM_UA_O_CFY_SUTA = Off
ERM_UA_O_CFY_RNS = Off
ERM_UA_O_LFY_FRS = Off
ERM_UA_O_CFY_FRS = Off

Code:

Begin
        chkERM_UA_O_TWA.Checked := true;
        chkERM_UA_O_AUT.Checked := false;
        chkERM_UA_O_RNS.Checked := false;
        chkERM_UA_O_UFRD.Checked := false;
        chkERM_UA_O_FRS.Checked := false;
        chkERM_UA_O_UFN.Checked := false;

        chkERM_UA_O_CFY_SUTA.Checked := false;
        chkERM_UA_O_CFY_RNS.Checked := false;
        chkERM_UA_O_LFY_FRS.Checked := false;
        chkERM_UA_O_CFY_FRS.Checked := false;
      end;

3. State ERM_UA_S_SAIE (Slow Accepted Initiated ERM)

Output Indicators

ERM_UA_O_TWA = Off
ERM_UA_O_AUT = ON
ERM_UA_O_RNS = Off
ERM_UA_O_UFRD= Off
ERM_UA_O_FRS = Off
ERM_UA_O_UFN = Off

Input Signals

ERM_UA_I_TWA = Off
ERM_UA_I_UFRD = Off
ERM_UA_I_UFN = Off

Output Signals

ERM_UA_O_CFY_SUTA = ON
ERM_UA_O_CFY_RNS = Off
ERM_UA_O_LFY_FRS = Off
ERM_UA_O_CFY_FRS = Off

Code:

Begin
        chkERM_UA_O_TWA.Checked := false;
        chkERM_UA_O_AUT.Checked := true;
        chkERM_UA_O_RNS.Checked := false;
        chkERM_UA_O_UFRD.Checked := false;
        chkERM_UA_O_FRS.Checked := false;
        chkERM_UA_O_UFN.Checked := false;

        chkERM_UA_O_CFY_SUTA.Checked := true;
        chkERM_UA_O_CFY_RNS.Checked := false;
        chkERM_UA_O_LFY_FRS.Checked := false;
        chkERM_UA_O_CFY_FRS.Checked := false;
      end;

4. State ERM_UA_S_FDIC (Fast Dispatch Initiated CFY)

Output Indicators

ERM_UA_O_TWA = Off
ERM_UA_O_AUT = Off
ERM_UA_O_RNS = Off
ERM_UA_O_UFRD= ON
ERM_UA_O_FRS = Off
ERM_UA_O_UFN = Off

Input Signals

ERM_UA_I_TWA = Off
ERM_UA_I_UFRD = ON
ERM_UA_I_UFN = Off

Output Signals

ERM_UA_O_CFY_SUTA = Off
ERM_UA_O_CFY_RNS = Off
ERM_UA_O_LFY_FRS = Off
ERM_UA_O_CFY_FRS = Off

Code:

Begin
        chkERM_UA_O_TWA.Checked := false;
        chkERM_UA_O_AUT.Checked := false;
        chkERM_UA_O_RNS.Checked := false;
        chkERM_UA_O_UFRD.Checked := true;
        chkERM_UA_O_FRS.Checked := false;
        chkERM_UA_O_UFN.Checked := false;

        chkERM_UA_O_CFY_SUTA.Checked := false;
        chkERM_UA_O_CFY_RNS.Checked := false;
        chkERM_UA_O_LFY_FRS.Checked := false;
        chkERM_UA_O_CFY_FRS.Checked := false;
      end;

5. State ERM_UA_S_FRSE (Fast Route Set initated ERM)

Output Indicators

ERM_UA_O_TWA = Off
ERM_UA_O_AUT = Off
ERM_UA_O_RNS = Off
ERM_UA_O_UFRD= Off
ERM_UA_O_FRS = ON
ERM_UA_O_UFN = Off

Input Signals

ERM_UA_I_TWA = Off
ERM_UA_I_UFRD = Off
ERM_UA_I_UFN = Off

Output Signals

ERM_UA_O_CFY_SUTA = Off
ERM_UA_O_CFY_RNS = Off
ERM_UA_O_LFY_FRS = ON
ERM_UA_O_CFY_FRS = ON

Code:

Begin
        chkERM_UA_O_TWA.Checked := false;
        chkERM_UA_O_AUT.Checked := false;
        chkERM_UA_O_RNS.Checked := false;
        chkERM_UA_O_UFRD.Checked := false;
        chkERM_UA_O_FRS.Checked := true;
        chkERM_UA_O_UFN.Checked := false;

        chkERM_UA_O_CFY_SUTA.Checked := false;
        chkERM_UA_O_CFY_RNS.Checked := false;
        chkERM_UA_O_LFY_FRS.Checked := true;
        chkERM_UA_O_CFY_FRS.Checked := true;
      end;

6. State ERM_UA_S_FAIL (Fast train Accepted Initated LFY)

Output Indicators

ERM_UA_O_TWA = Off
ERM_UA_O_AUT = Off
ERM_UA_O_RNS = Off
ERM_UA_O_UFRD= Off
ERM_UA_O_FRS = Off
ERM_UA_O_UFN = ON

Input Signals

ERM_UA_I_TWA = Off
ERM_UA_I_UFRD = Off
ERM_UA_I_UFN = ON

Output Signals

ERM_UA_O_CFY_SUTA = Off
ERM_UA_O_CFY_RNS = Off
ERM_UA_O_LFY_FRS = Off
ERM_UA_O_CFY_FRS = Off

Code:

Begin
        chkERM_UA_O_TWA.Checked := false;
        chkERM_UA_O_AUT.Checked := false;
        chkERM_UA_O_RNS.Checked := false;
        chkERM_UA_O_UFRD.Checked := false;
        chkERM_UA_O_FRS.Checked := false;
        chkERM_UA_O_UFN.Checked := true;

        chkERM_UA_O_CFY_SUTA.Checked := false;
        chkERM_UA_O_CFY_RNS.Checked := false;
        chkERM_UA_O_LFY_FRS.Checked := false;
        chkERM_UA_O_CFY_FRS.Checked := false;
      end;

Valid State Transitions

State 0 ERM_UA_S_INIT
State 1 ERM_UA_S_RSIE
State 2 ERM_UA_S_SDIC
State 3 ERM_UA_S_SAIE
State 4 ERM_UA_S_FDIC
State 5 ERM_UA_S_FRSE
State 6 ERM_UA_S_FAIL

State 0 --> State 1 Trigger Button Press ERM_UA_I_RNS
State 1 --> State 2 Trigger Input Signal ERM_UA_I_TWA = ON
State 2 --> State 3 Trigger Button Press ERM_UA_I_AUT
State 3 --> State 1 Trigger Button Press ERM_UA_I_RNS

State 1 --> State 4 Trigger Input Signal ERM_UA_I_UFRD
State 4 --> State 5 Trigger Button Press ERM_UA_I_FRS = ON
State 5 --> State 6 Trigger Input Signal ERM_UA_I_UFN = ON
State 6 --> State 1 Trigger Button Press ERM_UA_I_RNS

P4 Modeller · Nov 14, 2013

Panel ERM_UD

Steve Please Read Notes (Concerns) about this panel at end of this post.
NOTE also that State Identifiers are incorrect for this panel and have been changed ( this
may be because its easier to code, in which case i can live with that. Identifiers changed in Red)

0. State ERM_UD_S_INIT (Initial)

Output Indicators

ERM_UD_O_TRD = Off
ERM_UD_O_TA = Off
ERM_UD_O_ANS = Off

Input Signals

ERM_UD_I_UTA = Off
ERM_UD_I_ANS = Off

Output Signals

ERM_UD_O_LFY_STRD = Off

Code:

Begin
        chkERM_UD_O_TRD.Checked := false;
        chkERM_UD_O_TA.Checked := false;
        chkERM_UD_O_ANS.Checked := false;
        
        chkERM_UD_O_LFY_STRD.Checked := false;
    end;

1. State ERM_UD_S_RSIL (Ready Service next Initiated LFY) [ NOT RSIE]

Output Indicators

ERM_UD_O_TRD = Off
ERM_UD_O_TA = Off
ERM_UD_O_ANS = ON

Input Signals

ERM_UD_I_UTA = Off
ERM_UD_I_ANS = ON

Output Signals

ERM_UD_O_LFY_STRD = Off

Code:

Begin
        chkERM_UD_O_TRD.Checked := false;
        chkERM_UD_O_TA.Checked := false;
        chkERM_UD_O_ANS.Checked := true;
        
        chkERM_UD_O_LFY_STRD.Checked := false;
    end;

2. State ERM_UD_S_SDIE (Slow Dispatch ready Initiated ERM) [ NOT SDIC]

Output Indicators

ERM_UD_O_TRD = ON
ERM_UD_O_TA = Off
ERM_UD_O_ANS = Off

Input Signals

ERM_UD_I_UTA = Off
ERM_UD_I_ANS = Off

Output Signals

ERM_UD_O_LFY_STRD = ON

Code:

Begin
        chkERM_UD_O_TRD.Checked := true;
        chkERM_UD_O_TA.Checked := false;
        chkERM_UD_O_ANS.Checked := false;
        
        chkERM_UD_O_LFY_STRD.Checked := true;
    end;

3. State ERM_UD_S_SAIL (Slow Accepted Initiated LFY) [NOT SAIE]

Output Indicators

ERM_UD_O_TRD = Off
ERM_UD_O_TA = ON
ERM_UD_O_ANS = Off

Input Signals

ERM_UD_I_UTA = ON
ERM_UD_I_ANS = Off

Output Signals

ERM_UD_O_LFY_STRD = Off

Code:

Begin
        chkERM_UD_O_TRD.Checked := false;
        chkERM_UD_O_TA.Checked := true;
        chkERM_UD_O_ANS.Checked := false;
        
        chkERM_UD_O_LFY_STRD.Checked := false;
    end;

STATES 4 TO 6 DO NOT APPLY TO THIS PANEL AS THEY ARE FAST SERVICES (see note at bottom of this post)

4. State ERM_UD_S_FDIC (Fast Dispatch Initiated CFY)

Output Indicators

ERM_UD_O_TRD = Off
ERM_UD_O_TA = Off
ERM_UD_O_ANS = Off

Input Signals

ERM_UD_I_UTA = Off
ERM_UD_I_ANS = Off

Output Signals

ERM_UD_O_LFY_STRD = Off

Code:

Begin
        chkERM_UD_O_TRD.Checked := false;
        chkERM_UD_O_TA.Checked := false;
        chkERM_UD_O_ANS.Checked := false;
        
        chkERM_UD_O_LFY_STRD.Checked := false;
    end;

5. State ERM_UD_S_FRSE (Fast Route Set initated ERM)

Output Indicators

ERM_UD_O_TRD = Off
ERM_UD_O_TA = Off
ERM_UD_O_ANS = Off

Input Signals

ERM_UD_I_UTA = Off
ERM_UD_I_ANS = Off

Output Signals

ERM_UD_O_LFY_STRD = Off

Code:

Begin
        chkERM_UD_O_TRD.Checked := false;
        chkERM_UD_O_TA.Checked := false;
        chkERM_UD_O_ANS.Checked := false;
        
        chkERM_UD_O_LFY_STRD.Checked := false;
    end;

6. State ERM_UD_S_FAIL (Fast train Accepted Initated LFY)

Output Indicators

ERM_UD_O_TRD = Off
ERM_UD_O_TA = Off
ERM_UD_O_ANS = Off

Input Signals

ERM_UD_I_UTA = Off
ERM_UD_I_ANS = Off

Output Signals

ERM_UD_O_LFY_STRD = Off

Code:

Begin
        chkERM_UD_O_TRD.Checked := false;
        chkERM_UD_O_TA.Checked := false;
        chkERM_UD_O_ANS.Checked := false;
        
        chkERM_UD_O_LFY_STRD.Checked := false;
    end;

State 0 ERM_UD_S_INIT
State 1 ERM_UD_S_RSIL
State 2 ERM_UD_S_SDIE
State 3 ERM_UD_S_SAIL
State 4 ERM_UD_S_FDIC
State 5 ERM_UD_S_FRSE
State 6 ERM_UD_S_FAIL

State 0 --> State 1 Trigger Input Signal ERM_UD_I_ANS = ON
State 1 --> State 2 Trigger Button Press ERM_UD_I_TRD
State 2 --> State 3 Trigger Input Signal ERM_UA_I_UTA = ON
State 3 --> State 1 Trigger Input Signal ERM_UD_I_ANS = ON

NOTES (CONCERNS)

At present this panel goes to "illegal state" when States ERM_UD_S_FDIC, ERM_UD_S_FRSE, ERM_UD_S_FAIL. I've been wondering if this would cause the whole state machine to stop. After some thought, i wonder if it would be better to have signals go to this panel for these states from the associated panels and just cycle through the states with no outputs indicators . Alternatively i could add provision for a new output indicator "fast service panel not in use".

My reasoning behind this decision is that a fast service must be preceded by State ERM_UD_S_RSIL and to exit the fast service routine it must go back to this State. If we cycle through the "fast states" the same as the other panels we can put this panel in "limbo" mode (technical term lmao) until such time as ERM_UD_S_RSIL is reached post "fast service".... does that make sense ?

SO in this post i have set all the input/outputs to Off/False for these states ???

You will know how (if needed at all) best to remedy this

P4 Modeller · Nov 14, 2013

As per previous post State Identifiers changed in Red

Panel LFY_UA

1. Output Signal LFY_UA_O_ERM_UFA typo error ....to ERM_DA_I_UFN should read ERM_UA_I_UFN

0. State LFY_UA_S_INIT (Initial)

Output Indicators

LFY_UA_O_TWA = Off
LFY_UA_O_UTA = Off
LFY_UA_O_RNS = Off
LFY_UA_O_UFRD = Off
LFY_UA_O_FRS = Off
LFY_UA_O_UFA = Off

Input Signals

LFY_UA_I_STRD = Off
LFY_UA_I_FSRD = Off
LFY_UA_I_FRS = Off

Output Signals

LFY_UA_O_ERM_SUTA = Off
LFY_UA_O_ERM_RNS = Off
LFY_UA_O_CFY_UFA = Off
LFY_UA_O_ERM_UFA = Off

Code:

Begin
        chkLFY_UA_O_TWA.Checked := false;
        chkLFY_UA_O_UTA.Checked := false;
        chkLFY_UA_O_RNS.Checked := false;
        chkLFY_UA_O_UFRD.Checked := false;
        chkLFY_UA_O_FRS.Checked := false;
        chkLFY_UA_O_UFA.Checked := false;
        
        chkLFY_UA_O_ERM_SUTA.Checked := false;
        chkLFY_UA_O_ERM_RNS.Checked := false;
        chkLFY_UA_O_CFY_UFA.Checked := false;
        chkLFY_UA_O_ERM_UFA.Checked := false;
    end;

1. State LFY_UA_S_RSIL (Ready Service next Initiated LFY)

Output Indicators

LFY_UA_O_TWA = Off
LFY_UA_O_UTA = Off
LFY_UA_O_RNS = ON
LFY_UA_O_UFRD = Off
LFY_UA_O_FRS = Off
LFY_UA_O_UFA = Off

Input Signals

LFY_UA_I_STRD = Off
LFY_UA_I_FSRD = Off
LFY_UA_I_FRS = Off

Output Signals

LFY_UA_O_ERM_SUTA = Off
LFY_UA_O_ERM_RNS = ON
LFY_UA_O_CFY_UFA = Off
LFY_UA_O_ERM_UFA = Off

Code:

Begin
        chkLFY_UA_O_TWA.Checked := false;
        chkLFY_UA_O_UTA.Checked := false;
        chkLFY_UA_O_RNS.Checked := true;
        chkLFY_UA_O_UFRD.Checked := false;
        chkLFY_UA_O_FRS.Checked := false;
        chkLFY_UA_O_UFA.Checked := false;
        
        chkLFY_UA_O_ERM_SUTA.Checked := false;
        chkLFY_UA_O_ERM_RNS.Checked := true;
        chkLFY_UA_O_CFY_UFA.Checked := false;
        chkLFY_UA_O_ERM_UFA.Checked := false;
    end;

2. State LFY_UA_S_SDIE (Slow Dispatch ready Initiated ERM)

Output Indicators

LFY_UA_O_TWA = ON
LFY_UA_O_UTA = Off
LFY_UA_O_RNS = Off
LFY_UA_O_UFRD = Off
LFY_UA_O_FRS = Off
LFY_UA_O_UFA = Off

Input Signals

LFY_UA_I_STRD = ON
LFY_UA_I_FSRD = Off
LFY_UA_I_FRS = Off

Output Signals

LFY_UA_O_ERM_SUTA = Off
LFY_UA_O_ERM_RNS = Off
LFY_UA_O_CFY_UFA = Off
LFY_UA_O_ERM_UFA = Off

Code:

Begin
        chkLFY_UA_O_TWA.Checked := true;
        chkLFY_UA_O_UTA.Checked := false;
        chkLFY_UA_O_RNS.Checked := false;
        chkLFY_UA_O_UFRD.Checked := false;
        chkLFY_UA_O_FRS.Checked := false;
        chkLFY_UA_O_UFA.Checked := false;
        
        chkLFY_UA_O_ERM_SUTA.Checked := false;
        chkLFY_UA_O_ERM_RNS.Checked := false;
        chkLFY_UA_O_CFY_UFA.Checked := false;
        chkLFY_UA_O_ERM_UFA.Checked := false;
    end;

3. State LFY_UA_S_SAIL (Slow Accepted Initiated LFY)

Output Indicators

LFY_UA_O_TWA = Off
LFY_UA_O_UTA = ON
LFY_UA_O_RNS = Off
LFY_UA_O_UFRD = Off
LFY_UA_O_FRS = Off
LFY_UA_O_UFA = Off

Input Signals

LFY_UA_I_STRD = Off
LFY_UA_I_FSRD = Off
LFY_UA_I_FRS = Off

Output Signals

LFY_UA_O_ERM_SUTA = ON
LFY_UA_O_ERM_RNS = Off
LFY_UA_O_CFY_UFA = Off
LFY_UA_O_ERM_UFA = Off

Code:

Begin
        chkLFY_UA_O_TWA.Checked := false;
        chkLFY_UA_O_UTA.Checked := true;
        chkLFY_UA_O_RNS.Checked := false;
        chkLFY_UA_O_UFRD.Checked := false;
        chkLFY_UA_O_FRS.Checked := false;
        chkLFY_UA_O_UFA.Checked := false;
        
        chkLFY_UA_O_ERM_SUTA.Checked := true;
        chkLFY_UA_O_ERM_RNS.Checked := false;
        chkLFY_UA_O_CFY_UFA.Checked := false;
        chkLFY_UA_O_ERM_UFA.Checked := false;
    end;

4. State LFY_UA_S_FDIC (Fast Dispatch Initiated CFY)

Output Indicators

LFY_UA_O_TWA = Off
LFY_UA_O_UTA = Off
LFY_UA_O_RNS = Off
LFY_UA_O_UFRD = ON
LFY_UA_O_FRS = Off
LFY_UA_O_UFA = Off

Input Signals

LFY_UA_I_STRD = Off
LFY_UA_I_FSRD = ON
LFY_UA_I_FRS = Off

Output Signals

LFY_UA_O_ERM_SUTA = Off
LFY_UA_O_ERM_RNS = Off
LFY_UA_O_CFY_UFA = Off
LFY_UA_O_ERM_UFA = Off

Code:

Begin
        chkLFY_UA_O_TWA.Checked := false;
        chkLFY_UA_O_UTA.Checked := false;
        chkLFY_UA_O_RNS.Checked := false;
        chkLFY_UA_O_UFRD.Checked := true;
        chkLFY_UA_O_FRS.Checked := false;
        chkLFY_UA_O_UFA.Checked := false;
        
        chkLFY_UA_O_ERM_SUTA.Checked := false;
        chkLFY_UA_O_ERM_RNS.Checked := false;
        chkLFY_UA_O_CFY_UFA.Checked := false;
        chkLFY_UA_O_ERM_UFA.Checked := false;
    end;

5. State LFY_UA_S_FRSE (Fast Route Set initated ERM)

Output Indicators

LFY_UA_O_TWA = Off
LFY_UA_O_UTA = Off
LFY_UA_O_RNS = Off
LFY_UA_O_UFRD = ON
LFY_UA_O_FRS = ON
LFY_UA_O_UFA = Off

Input Signals

LFY_UA_I_STRD = Off
LFY_UA_I_FSRD = Off
LFY_UA_I_FRS = ON

Output Signals

LFY_UA_O_ERM_SUTA = Off
LFY_UA_O_ERM_RNS = Off
LFY_UA_O_CFY_UFA = Off
LFY_UA_O_ERM_UFA = Off

Code:

Begin
        chkLFY_UA_O_TWA.Checked := false;
        chkLFY_UA_O_UTA.Checked := false;
        chkLFY_UA_O_RNS.Checked := false;
        chkLFY_UA_O_UFRD.Checked := true;
        chkLFY_UA_O_FRS.Checked := true;
        chkLFY_UA_O_UFA.Checked := false;
        
        chkLFY_UA_O_ERM_SUTA.Checked := false;
        chkLFY_UA_O_ERM_RNS.Checked := false;
        chkLFY_UA_O_CFY_UFA.Checked := false;
        chkLFY_UA_O_ERM_UFA.Checked := false;
    end;

6. State LFY_UA_S_FAIL (Fast train Accepted Initated LFY)

Output Indicators

LFY_UA_O_TWA = Off
LFY_UA_O_UTA = Off
LFY_UA_O_RNS = Off
LFY_UA_O_UFRD = Off
LFY_UA_O_FRS = Off
LFY_UA_O_UFA = ON

Input Signals

LFY_UA_I_STRD = Off
LFY_UA_I_FSRD = Off
LFY_UA_I_FRS = Off

Output Signals

LFY_UA_O_ERM_SUTA = Off
LFY_UA_O_ERM_RNS = Off
LFY_UA_O_CFY_UFA = ON
LFY_UA_O_ERM_UFA = ON

Code:

Begin
        chkLFY_UA_O_TWA.Checked := false;
        chkLFY_UA_O_UTA.Checked := false;
        chkLFY_UA_O_RNS.Checked := false;
        chkLFY_UA_O_UFRD.Checked := false;
        chkLFY_UA_O_FRS.Checked := false;
        chkLFY_UA_O_UFA.Checked := true;
        
        chkLFY_UA_O_ERM_SUTA.Checked := false;
        chkLFY_UA_O_ERM_RNS.Checked := false;
        chkLFY_UA_O_CFY_UFA.Checked := true;
        chkLFY_UA_O_ERM_UFA.Checked := true;
    end;

State 0 LFY_UA_S_INIT
State 1 LFY_UA_S_RSIL
State 2 LFY_UA_S_SDIE
State 3 LFY_UA_S_SAIL
State 4 LFY_UA_S_FDIC
State 5 LFY_UA_S_FRSE
State 6 LFY_UA_S_FAIL

State 0 --> State 1 Trigger Button Press LFY_UA_I_RNS
State 1 --> State 2 Trigger Input Signal LFY_UA_I_STRD = ON
State 2 --> State 3 Trigger Button Press LFY_UA_I_UTA
State 3 --> State 1 Trigger Button Press LFY_UA_I_RNS

State 1 --> State 4 Trigger Button Press LFY_UA_I_FRSD
State 4 --> State 5 Trigger Input Signal LFY_UA_I_FRS = ON
State 5 --> State 6 Trigger Button Press LFY_UA_I_UFA
State 6 --> State 1 Trigger Button Press LFY_UA_I_RNS

P4 Modeller · Nov 14, 2013

Hi Steve,

Spent 6hrs on these so far. Found it easier to post in code form rather than "this should be changed to this form".

I am still going through the panels trying to post changes needed so this is very much work still in progress

I think i have grasped the code so i have completed this for all panels as i feel it should work

Tired Eyes...Fried Brain ......Time for a Break

Mark

(*steve*) · Nov 15, 2013

That is an enormous amount of work!

I will get you a new version during the weekend. Let's see if it goes better!

P4 Modeller · Nov 15, 2013

Hi Steve

Produced a checklist in order to complete the list needed to be changed

Edit Notes Added

Before you look at this i need to explain a few things about these "checklist"

1. If marked as [Checked] this means everything else
in this category should be [unchecked]

2. This is what i expect to see on each panel when in "Manual" mode.
Obviously when in "Automatic" mode Steps marked with:

Trigger to Next State = Input Signal xxx_UA_O_xx_xxx @ xxx_UD_I_xxx --> State S-xxx

panels recieving that input signal will go to their next state.

3. When i have posted:

Trigger to Next State = Input Control xxx_UA_I_xxx --> State S-xxxx

I have also put : Input Controls = xxx_UA_I_xxx [Checked]
This means user has pressed button and the outcome is listed in:

Output Indications:
Input Signals:
Output Signals:

4. This seems logical for my secanrio but for the sake of it (and my reference):
(a) If a state has an Input Control it must have at least one Output Signal
(b) If a state has an Input Signal it cannot have an Input Control
(c) A Output Indication must be present on each state except S_INIT

5. For Clarity as there are 2 ERM Panels i have annotated on Signals (to ERM_xx Panel)
This is because there is at least one instance where it could mean either panel.

CFY_UD Panel

Code:

CFY_UD Panel

When in state 

S_INIT --> 	Input Controls = [All Unchecked]
	   	Output Indications = [All Unchecked]
	   	Input Signals= [All Unchecked]
	   	Output Signals  = [All Unchecked]

Trigger to Next State = Input Signal ERM_UA_O_CFY_RNS @ CFY_UD_I_ANS --> State S-RSIE

S_RSIE -->	Input Controls = [All Unchecked]
	   	Output Indications = CFY_UD_O_ANS [Checked]
	   	Input Signals= CFY_UD_I_ANS [Checked]
	   	Output Signals  = [All Unchecked]

Either:

Trigger to Next State = Input Control CFY_UD_I_TRD --> State S_SDIC 

S_SDIC -->	Input Controls = CFY_UD_I_TRD [Checked]
	   	Output Indications = CFY_UD_O_TRD [Checked]
	   	Input Signals= [All Unchecked]
	   	Output Signals  = CFY_UD_O_ERM_STRD [Checked] ( to ERM_UA)

Trigger to Next State = Input Signal ERM_UA_O_CFY_SUTA @ CFY_UD_I_STA --> State S-SAIE

S_SAIE -->	Input Controls = [All Unchecked]
	   	Output Indications = CFY_UD_O_TA [Checked]
	   	Input Signals= CFY_UD_I_STA [Checked]
	   	Output Signals  = [All Unchecked]

Or:

Trigger to Next State = Input Control CFY_UD_I_FRSD --> State S_FDIC


S_FDIC -->	Input Controls = CFY_UD_O_FRSD [Checked]
	   	Output Indications = CFY_UD_O_FRSD [Checked]
	   	Input Signals= [All Unchecked]
	   	Output Signals  = CFY_UD_O_ERM_FRSD [Checked] (to ERM_UA)
				CFY_UD_O_LFY_FRSD [Checked]

Trigger to Next State = Input Signal ERM_UA_O_CFY_FRSE @ CFY_UD_I_FRS --> State S-FRSE

S_FRSE -->	Input Controls = [All Unchecked]
	   	Output Indications = CFY_UD_O_FRS [Checked]
	   	Input Signals=CFY_UD_I_FRS  [Checked]
	   	Output Signals  = [All Unchecked]

Trigger to Next State = Input Signal LFY_UA_O_CFY_UFA @ CFY_UD_I_FTA --> State S-FAIL

S_FAIL -->	Input Controls = [All Unchecked]
	   	Output Indications = CFY_UD_O_FTA [Checked]
	   	Input Signals= CFY_UD_I_FTA [Checked]
	   	Output Signals  = [All Unchecked]

ERM_UA Panel

Code:

ERM_UA Panel

When in state

S_INIT --> 	Input Controls = [All Unchecked]
	   	Output Indications = [All Unchecked]
	   	Input Signals= [All Unchecked]
	   	Output Signals  = [All Unchecked]

Trigger to Next State = Input Control ERM_UA_I_RNS  --> State S-RSIE


S_RSIE --> 	Input Controls = ERM_UA_I_RNS [Checked]
	   	Output Indications = ERM_UA_O_RNS [Checked]
	   	Input Signals= [All Unchecked]
	   	Output Signals  = ERM_UA_O_CFY_RNS [Checked]

Either:
Trigger to Next State = Input Signal CFY_UD_O_ERM_STRD @ ERM_UA_I_TWA --> State S-SDIC

S_SDIC --> 	Input Controls = [All Unchecked]
	   	Output Indications = ERM_UA_O_TWA [All Unchecked]
	   	Input Signals= ERM_UA_I_TWA [Checked]
	   	Output Signals  = [All Unchecked]

Trigger to Next State = Input Control ERM_UA_I_AUT  --> State S-SAIE

S_SAIE --> 	Input Controls = ERM_UA_I_AUT [Checked]
	   	Output Indications = ERM_UA_O_AUT [Checked]
	   	Input Signals= [All Unchecked]
	   	Output Signals  = ERM_UA_O_CFY_AUT [Checked]

Or:
Trigger to Next State = Input Signal CFY_UD_O_ERM_FRSD @ ERM_UA_I_UFRD --> State S-FDIC


S_FDIC --> 	Input Controls = [All Unchecked]
	   	Output Indications = ERM_UA_O_UFRD [All Unchecked]
	   	Input Signals= ERM_UA_I_UFRD [Checked]
	   	Output Signals  = [All Unchecked]

Trigger to Next State = Input Control ERM_UA_I_FRS  --> State S-FRSE

S_FRSE --> 	Input Controls = ERM_UA_I_FRS [Checked]
	   	Output Indications = ERM_UA_O_FRS [Checked]
	   	Input Signals= [All Unchecked]
	   	Output Signals = ERM_UA_O_CFY_FRS [Checked]
			            ERM_UA_O_LFY_FRS [Checked]

Trigger to Next State = Input Signal LFY_UA_O_ERM_UFA @ ERM_UA_I_UFN --> State S-FAIL


S_FAIL --> 	Input Controls = [All Unchecked]
	   	Output Indications = ERM_UA_O_UFN [Checked]
	   	Input Signals= ERM_UA_I_UFN [Checked]
	   	Output Signals  = [All Unchecked]

Will do the other 2 Panels 1st thing tomorrow

Mark

(*steve*) · Nov 16, 2013

Great! Posting from my phone right now but your stuff looks like it will translate well to my simulator

P4 Modeller · Nov 16, 2013

ERM_UD Panel

Code:

ERM_UD Panel

When in state

S_INIT --> 	Input Controls = [All Unchecked]
	   	Output Indications = [All Unchecked]
	   	Input Signals = [All Unchecked]
	   	Output Signals  = [All Unchecked]

Trigger to Next State = Input Signal LFY_UA_O_ERM_RNS @ ERM_UD_I_ANS --> State S-RSIL


S_RSIL  -->	Input Controls = [All Unchecked]
	   	Output Indications = ERM_UD_O_ANS [Checked]
	   	Input Signals = ERM_UD_I_ANS  [Checked]
	   	Output Signals  = [All Unchecked]

Trigger to Next State = Input Control ERM_UD_I_TRD  --> State S-SDIE


S_SDIE  -->	Input Controls = ERM_UD_I_TRD  [Checked]
	   	Output Indications = ERM_UD_O_TRD [Checked]
	   	Input Signals = [All Unchecked]
	   	Output Signals  = ERM_UD_O_LFY_STRD [Checked] 

Trigger to Next State = Input Signal LFY_UA_O_ERM_SUTA @ ERM_UD_I_UTA --> State S-SAIL


S_SAIL  -->	Input Controls = [All Unchecked]
	   	Output Indications = ERM_UD_O_UTA [Checked]
	   	Input Signals= ERM_UD_I_UTA [Checked]
	   	Output Signals  = [All Unchecked]

LFY_UA Panel

Code:

LFY_UA Panel

When in state

S_INIT --> 	Input Controls = [All Unchecked]
	   	Output Indications = [All Unchecked]
	   	Input Signals= [All Unchecked]
	   	Output Signals  = [All Unchecked]

Trigger to Next State = Input Control LFY_UA_I_RNS  --> State S-RSIL


S_RSIL  -->	Input Controls = LFY_UA_I_RNS [Checked]
	   	Output Indications = LFY_UA_O_RNS [Checked]
	   	Input Signals= [All Unchecked]
	   	Output Signals  = LFY_UA_O_ERM_ANS [Checked] (to ERM_UD Panel)

Trigger to Next State = Input Signal ERM_UD_O_LFY_STRD @ LFY_UA_I_STRD --> State S-SDIE


S_SDIE  -->	Input Controls = [All Unchecked]
	   	Output Indications =LFY_UA_O_TWA [Checked]
	   	Input Signals= LFY_UA_I_STRD [Checked]
	   	Output Signals  = [All Unchecked]

Trigger to Next State = Input Control LFY_UA_I_UTA  --> State S-SAIL


S_SAIL  -->	Input Controls = LFY_UA_I_UTA [Checked]
	   	Output Indications = LFY_UA_O_UTA [Checked]
	   	Input Signals= [All Unchecked]
	   	Output Signals  = LFY_UA_O_ERM_SUTA [Checked]  (to ERM_UD Panel)

Trigger to Next State = Input Signal CFY_UD_O_LFY_FSRD @ LFY_UA_I_FSRD --> State S-FDIC


S_FDIC -->	Input Controls = [All Unchecked]
	   	Output Indications = LFY_UA_O_UFRD [Checked]
	   	Input Signals = LFY_UA_I_FSRD [Checked]
	   	Output Signals  = [All Unchecked]

Trigger to Next State = Input Signal ERM_UA_O_ERM_FRS @ LFY_UA_I_FRS --> State S-FRSE


S_FRSE -->	Input Controls = [All Unchecked]
	   	Output Indications = LFY_UA_O_FRS [Checked]
				    LFY_UA_O_UFRD [Checked]
	   	Input Signals = LFY_UA_I_FRS [Checked]
	   	Output Signals  = [All Unchecked]

Trigger to Next State = Input Control LFY_UA_I_UFA  --> State S-FAIL

S_FAIL -->	Input Controls = LFY_UA_I_UFA [Checked]
	   	Output Indications = LFY_UA_O_UFA  [Checked]
	   	Input Signals = [All Unchecked]
	   	Output Signals  = LFY_UA_O_ERM_UFA [Checked] (to ERM_UA Panel)
				LFY_UA_O_CFY_UFA [Checked]

Mark

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Arduino control of model train signalling (was: LED Power Supply for Control Panel)

Arduino control of model train signalling (was: LED Power Supply for Control Panel)

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