Ok well i re read your posts
You now need to take these and rewrite them in terms of states and signals
And took the rewrite as "keep in separate movements for the time being"
And
At this point you will have created each panels states and transitions, then walked through them with the valid examples.
As when happy transfer to create each panel states and transitions
Haven't got this far yet.... BUT whilst what i wrote in "The Narratives" is what IS supposed to happen ... I have met some strong resistance ..lol
Code:
SLOW TRAIN MOVEMENT [LFY_DD] TO [ERM_DA]
ERM DA STATES:
0 ERM_DA_S_INIT INITIAL
1 ERM_DA_S_RSIE READY NEXT SERVICE
2 ERM_ DA_S_SDIL SLOW DISPATCH
3 ERM_DA_S_SAIE SLOW ACCEPT
4 ERM_DA_S_FDIL FAST DISPATCH
5 ERM_DA_S_FRSE FAST ROUTE SET
6 ERM_DA_S_FAIC FAST ACCEPTED
LFY_DD_STATES
0 LFY_DD_S_INIT INITIAL
1 LFY_DD_S_RSIE READY NEXT SERVICE
2 LFY_ DD_S_SDIL SLOW DISPATCH
3 LFY_DD_S_SAIE SLOW ACCEPT
4 LFY_DD_S_FDIL FAST DISPATCH
5 LFY_DD_S_FRSE FAST ROUTE SET
6 LFY_DD_S_FAIC FAST ACCEPTED
1) STATES:
LFY_DD PANEL IN STATE 0 (LFY_DD_S_INIT) and
ERM_DA PANEL IN STATE 0 (ERM_DA_S_INIT)
Or
LFY_DD PANEL IN STATE 3 (LFY_DD_S_SAIE) and
ERM_DA PANEL IN STATE 3 (ERM_DA_S_SAIE)
ACTION:
ERM_DA OPERATOR press Input [ERM_DA_I_RNS]
TRANSITIONS:
ERM_DA PANEL TRANSITION to STATE 1 (ERM_DA_S_RSIE)
Asserting Signal [ERM_DA_O_LFY _RNS]
LFY_DD_PANEL TRANSITION to STATE 1 (LFY_DA_S_RSIE)
From Signal [ERM_DA_O_LFY_RNS] asserted at [LFY_DD_I_ANS]
2) STATES:
LFY_DD PANEL IN STATE 1 (LFY_DD_S_RSIE)
ERM_DA PANEL IN STATE 1 (ERM_DA_S_RSIE)
ACTION:
LFY_DD OPERATOR press Input [LFY_DD_I_TRD]
TRANSITIONS:
LFY_DD_PANEL TRANSITION to STATE 2 (LFY_DD_S-SDIL)
Asserting Signal [LFY_DD_O_ERM_STRD]
ERM_DA PANEL TRANSITION to STATE 2 (ERM_DA_S_SDIL)
From Signal [LFY_DD_O_ERM_STRD] asserted at [ERM_DA_I_TWA]
3) STATES:
LFY_DD PANEL IN STATE 2 (LFY_DD_S_SDIL)
ERM_DA PANEL IN STATE 2 (ERM_DA_S_SDIL)
ACTION:
ERM_DA OPERATOR press Input [ERM_DA_O_I_ADT]
TRANSITIONS:
ERM_DA PANEL TRANSITION to STATE 4 (ERM_DA_S_SAIE)
Asserting Signal [ERM_DA_O_LFY_STDA]
LFY_DD_PANEL TRANSITION to STATE 3 (LFY_DD_S_SAIE)
From Signal [ERM_DA_O_LFY_STDA] asserted at [LFY_DD_I _STA]
This works fine at the moment
Code:
SLOW TRAIN MOVEMENT [ERM_DD] TO [CFY_DA]
ERM DD STATES:
0 ERM_DD_S_INIT INITIAL
1 ERM_DD_S_RSIC READY NEXT SERVICE
2 ERM_DD_S_SDIE SLOW DISPATCH
3 ERM_DD_S_SAIC SLOW ACCEPT
CFY_DA_STATES
0 CFY_DA_S_INIT INITIAL
1 CFY_DA_S_RSIC READY NEXT SERVICE
2 CFY_DA_S_SDIE SLOW DISPATCH
3 CFY_DA_S_SAIC SLOW ACCEPT
4 CFY_DA_S_FDIL FAST DISPATCH
5 CFY_DA_S_FRSE FAST ROUTE SET
6 CFY_DA_S_FAIC FAST ACCEPTED
1) STATES:
ERM_DD PANEL IN STATE 0 (ERM_DD_S_INIIT) and
CFY_DA PANEL IN STATE 0 (CFY_DA_S_INIT)
Or
ERM_DD PANEL IN STATE 3 (ERM_DD_S_SAIC) and
CFY_DA PANEL IN STATE 3 (CFY_DA_S_SAIC)
ACTION:
CFY_DA OPERATOR press Input [ERM_DA_I_RNS]
TRANSITIONS:
CFY_DA PANEL TRANSITION to STATE 1 (CFY_DA_S_RSIC)
Asserting Signal [CFY_DA_O_ERM _RNS]
ERM_DD_PANEL TRANSITION to STATE 1 (ERM_DD_S_RSIC)
From Signal [CFY_DA_O_ERM_RNS] asserted at [ERM_DD_I_ANS]
2) STATES:
ERM_DD PANEL IN STATE 1 (ERM_DD_S_RSIC) and
CFY_DA PANEL IN STATE 1 (CFY_DA_S_RSIC)
ACTION:
ERM_DD OPERATOR press Input [ERM_DD_I_TRD]
TRANSITIONS:
ERM_DD PANEL TRANSITION to STATE 2 (ERM_DD_S_SDIE)
Asserting Signal [ERM_DD_O_CFY _STRD]
CFY_DA_PANEL TRANSITION to STATE 2 (CFY_DA_S_SDIE)
From Signal [CFY_DA_O_ERM_STRD] asserted at [CFY_DA_I_STRD]
3) STATES:
ERM_DD PANEL IN STATE 1 (ERM_DD_S_SDIE) and
CFY_DA PANEL IN STATE 1 (CFY_DA_S_SDIE)
ACTION:
CFY_DA OPERATOR press Input [CFY_DA_I_DTA]
TRANSITIONS:
CFY_DA PANEL TRANSITION to STATE 3 (CFY_DA_S_SAIC)
Asserting Signal [CFY_DA_O_ERM _SDTA]
ERM_DD_PANEL TRANSITION to STATE 3 (ERM_DA_S_SAIC)
From Signal [CFY_DA_O_ERM_SDTA] asserted at [ERM_DD_I_DTA]
This too
The problem lies in the Slow to Fast Interface.
Code:
FAST TRAIN MOVEMENTS [LFY_DD] TO [CFY_DA]
LFY_DD_STATES
0 LFY_DD_S_INIT INITIAL
1 LFY_DD_S_RSIE READY NEXT SERVICE
2 LFY_ DD_S_SDIL SLOW DISPATCH *NOT USED IN FAST TRAIN*
3 LFY_DD_S_SAIE SLOW ACCEPT *NOT USED IN FAST TRAIN*
4 LFY_DD_S_FDIL FAST DISPATCH
5 LFY_DD_S_FRSE FAST ROUTE SET
6 LFY_DD_S_FAIC FAST ACCEPTED
ERM DA STATES:
0 ERM_DA_S_INIT INITIAL
1 ERM_DA_S_RSIE READY NEXT SERVICE
2 ERM_ DA_S_SDIL SLOW DISPATCH *NOT USED IN FAST TRAIN*
3 ERM_DA_S_SAIE SLOW ACCEPT *NOT USED IN FAST TRAIN*
4 ERM_DA_S_FDIL FAST DISPATCH
5 ERM_DA_S_FRSE FAST ROUTE SET
6 ERM_DA_S_FAIC FAST ACCEPTED
CFY_DA_STATES
0 CFY_DA_S_INIT INITIAL
1 CFY_DA _S_RSIC READY NEXT SERVICE
2 CFY_DA _S_SDIE SLOW DISPATCH *NOT USED IN FAST TRAIN*
3 CFY_DA _S_SAIC SLOW ACCEPT *NOT USED IN FAST TRAIN*
4 CFY_DA _S_FDIL FAST DISPATCH
5 CFY_DA _S_FRSE FAST ROUTE SET
6 CFY_DA _S_FAIC FAST ACCEPTED
1) STATES:
LFY_DD PANEL IN STATE 1 (LFY_DD_S_RNS) and
ERM_DA PANEL IN STATE 1 (ERM_DA_S_RNS) and
CFY_DA PANEL IN STATE 1 (CFY_DA_S_RNS)
(can this be right as ERM_DD will also be in RNS when CFY-DA in RNS also what if ERM_DD and CFY DA not in RNS when input LFY_DD_I_FAST selected )
ACTION:
LFY_DD OPERATOR press Input [LFY_DD_I_FSRD]
TRANSITIONS:
LFY_DD PANEL TRANSITION to STATE 4 (LFY_DD_S_FDIL)
Asserting Signal [LFY_DD_O_ERM _FSRD]
Asserting Signal [LFY_DD_O_CFY_FSRD]
ERM_DA PANEL TRANSITION to STATE 4 (ERM_DA_S_FDIL)
From Signal [LFY_DD_O_ERM_FRSD] asserted at [ERM_DD_I_DFRD]
CFY_DA PANEL TRANSITION to STATE 4 (CFY_DA_S_FDIL)
From Signal [LFY_DD_O_CFY_FRSD] asserted at [ERM_DD_I_FSRD]
2) STATES:
LFY_DD PANEL IN STATE 4 (LFY_DD_S_FDIL) and
ERM_DA PANEL IN STATE 4 (ERM_DA_S_FDIL) and
CFY_DA PANEL IN STATE 4 (CFY_DA_S_FDIL)
ACTION:
ERM_DA OPERATOR press Input [ERM_DA_I_FRS]
TRANSITIONS:
ERM_DA PANEL TRANSITION to STATE 5 (ERM_DA_S_FRSE)
Asserting Signal [ERM_DA_O_LFY _FRS]
Asserting Signal [ERM_DA_O_CFY_FRS]
LFY_DD PANEL TRANSITION to STATE 5 (LFY_DD_S_FRSE)
From Signal [ERM_DA_O_LFY_FRS] asserted at [LFY_DD_I_FRS]
CFY_DA PANEL TRANSITION to STATE 5 (CFY_DA_S_FRSE)
From Signal [ERM_DA_O_CFY_FRS] asserted at [CFY_DA_I_FRS]
3) STATES:
LFY_DD PANEL IN STATE 4 (LFY_DD_S_FRSE) and
ERM_DA PANEL IN STATE 4 (ERM_DA_S_FRSE) and
CFY_DA PANEL IN STATE 4 (CFY_DA_S_FRSE)
ACTION:
CFY_DA OPERATOR press Input [CFY_DA_I_DFA]
TRANSITIONS:
CFY_DA PANEL TRANSITION to STATE 6 (CFY_DA_S_FAIC)
Asserting Signal [CFY_DA_O_LFY _DFA]
Asserting Signal CFY_DA_O_ERM_DFA]
LFY_DD PANEL TRANSITION to STATE 6 (LFY_DD_S_FAIC)
From Signal [CFY_DA_O_LFY_DFA] asserted at [LFY_DD_I_FTA]
ERM_DA PANEL TRANSITION to STATE 5 (ERM_DA_S_FAIC)
From Signal [CFY_DA_O_ERM_DFA] asserted at [CFY_DA_I_DFN]
4) STATES: Ready Next – Clear All Blocks
LFY_DD PANEL IN STATE 6 (LFY_DD_S_FAIC) and
ERM_DA PANEL IN STATE 6 (ERM_DA_S_FAIC) and
CFY_DA PANEL IN STATE 6 (CFY_DA_S_FAIC)
ACTION:
CFY_DA OPERATOR press Input [CFY_DA_I_RNS]
TRANSITIONS:
CFY_DA PANEL TRANSITION to STATE 1 (CFY_DA_S_RSIC)
Asserting Signal [CFY_DA_O_LFY _XYZ]
Asserting Signal [CFY_DA_O_ERM_DA _XYZ]
Asserting Signal [CFY_DA_O_ERM_DD _XYZ]
LFY_DD_PANEL TRANSITION to STATE 1 (LFY_DD_S_RSIC)
From Signal [CFY_DA_O_LFY_XYZ] asserted at [LFY_DD_I_XYZ]
ERM_DA_PANEL TRANSITION to STATE 1 (ERM_DA_S_RSIC)
From Signal [CFY_DA_O_ERM_DA _XYZ] asserted at [ERM_DA_I_XYZ]
ERM_DD_PANEL TRANSITION to STATE 1 (ERM_DD_S_RSIC)
From Signal [CFY_DA_O_ERM_DD _XYZ] asserted at [ERM_DD_I_XYZ]
5) STATES: Ready Next – Clear Own Block (LFY_DD and ERM-DA)
LFY_DD PANEL IN STATE 6 (LFY_DD_S_FAIC) and
ERM_DA PANEL IN STATE 6 (ERM_DA_S_FAIC)
ACTION:
ERM_DA OPERATOR press Input [ERM_DA_I_RNS]
TRANSITIONS:
ERM_DA PANEL TRANSITION to STATE 1 (ERM_DA_S_RSIE)
Asserting Signal [ERM_DA_O_LFY _RNS]
LFY_DD_PANEL TRANSITION to STATE 1 (LFY_DA_S_RSIE)
From Signal [ERM_DA_O_LFY_RNS] asserted at [LFY_DD_I_ANS]
6) STATES: Ready Next – Clear Own Block (ERM_DD and CFY-DA)
ERM_DD PANEL IN STATE 3 (ERM_DD_S_SAIC) and
CFY_DA PANEL IN STATE 3 (CFY_DA_S_SAIC)
ACTION:
CFY_DA OPERATOR press Input [ERM_DA_I_RNS]
TRANSITIONS:
CFY_DA PANEL TRANSITION to STATE 1 (CFY_DA_S_RSIC)
Asserting Signal [CFY_DA_O_ERM _RNS]
ERM_DD_PANEL TRANSITION to STATE 1 (ERM_DD_S_RSIC)
From Signal [CFY_DA_O_ERM_RNS] asserted at [ERM_DD_I_ANS]
So whats troubling me,
Well if LFY_DD decides to initiate a fast train movement.... but ERM_DD to CFY_DA are on a slow train movement... then what happens then. Is there a way to delay the input until the slow movement has been completed and the Instant a "ready next service" Is inputted at CFY the "Fast Train Sequence" is launched ??
The other thing that worries me is getting out of the fast train movement back to ready next service... mainly because ERM_DD is left out of the loop in "Fast Movements" .. One thought i had and i'm unsure if possible is to put ERM_DD in State 0 ( all lights off) during "fast movements".
The Only reason i say this is that the intention was that if a panel went to "Reset/Initial" state... the lights would go off...and the sequence would need to be started from scratch with a "Ready Next Service" Input.. this would also mean that there would be no recognised inputs from ERM_DD during fast movements.
The other idea was to have a set of "Ghost" inputs to ERM_DD that matched the fast sequence but had no "physical" outputs (LEDs)
What do you think ??
Oh ps i think state 7 is required because a seperate signal would need to be set on (XYZ in code) to signal all panels to go to "RNS" if CFY_DA actioned post "fast movements" this (signal) would not be so if ERM_DA actioned "Ready Next Service" first.
Mark
