5 Digit Digital stop watch using a MC14553b and TIL 311

[blures]

I havé access to a lm555 chip. Would this make a more accurate pulse? There is unfortunately no way I can get access to crystals at this time

 

[BobK]

Then you are not going to make a stopwatch with 0.01 second accuracy, and it would be a stretch to make 1 second accuracy over 10 minutes.

Bob

 

[blures]

Am I correct in assuming that I should leave pins 1,2,15(digit select), 10(latch enable), and 11(disable) on my mc14553 chips as a floating?

 

[blures]

Is there any good way to make a start stop button, out of a debounced button on the breadboard? The issue I keep running into is the fact that when you let go of the button, it will go back to the state before the button was pushed and I don't see a way of getting around that

 

[KrisBlueNZ]

You never leave inputs floating. The digit select pins are outputs, and you don't need them, so leave them unconnected, but Latch Enable (10) needs to be tied low and Clock Disable (11) needs to be tied low as well. Also pin 4 needs to be tied either low or high (doesn't matter which) and pin 3 must be floating.

For starting and stopping the timer, you need a flip-flop whose output represents the "running" status. A CD4013 or CD4027 is suitable. While the flip-flop's output is high, the 100 Hz clock is enabled through to the hundredths digit counter; while the flip-flop's output is low, the clock to the hundredths digit counter is gated off.

If you want a single start/stop button you can make the flip-flop toggle in response to the pulse from the pushbutton debouncer. Connect the debouncer to the flip-flop's clock input, then for a D flip-flop, connect D to Q-bar, and for a JK flip-flop, tie J and K both high. The flip-flop will toggle on each button press.

 

[blures]

You never leave inputs floating. The digit select pins are outputs, and you don't need them, so leave them unconnected, but Latch Enable (10) needs to be tied low and Clock Disable (11) needs to be tied low as well. Also pin 4 needs to be tied either low or high (doesn't matter which) and pin 3 must be floating.

For starting and stopping the timer, you need a flip-flop whose output represents the "running" status. A CD4013 or CD4027 is suitable. While the flip-flop's output is high, the 100 Hz clock is enabled through to the hundredths digit counter; while the flip-flop's output is low, the clock to the hundredths digit counter is gated off.

If you want a single start/stop button you can make the flip-flop toggle in response to the pulse from the pushbutton debouncer. Connect the debouncer to the flip-flop's clock input, then for a D flip-flop, connect D to Q-bar, and for a JK flip-flop, tie J and K both high. The flip-flop will toggle on each button press.

If I were to use a jk, would my clock pulse be coming in just before my jk that's where my debounced switch is, and then at Q I'm going into the my first binary counter?
And for my reset button, could I have the same flip flop going into the MR of each counter？

 

[KrisBlueNZ]

I don't understand your first question. The pushbutton feeds the debouncer which generates a short pulse (positive, because the 4013 and 4027 are both clocked on the rising edge), which goes into the flip-flop clock. The flip-flop controls the run/pause state of the circuit, so its output gates the 100 Hz clock into the first (hundredths of a second digit) counter.

The reset button doesn't need a flip-flop. It just needs to generate a pulse that feeds the MR inputs of all the counters. For the tens-of-seconds counter, an MR pulse is also needed when the count reaches 0110b as I explained earlier; you need to gate the reset button pulse with the output of the AND gate that detects 0110b and feed the gate output into the MR input for that counter.

 

[blures]

I don't understand your first question. The pushbutton feeds the debouncer which generates a short pulse (positive, because the 4013 and 4027 are both clocked on the rising edge), which goes into the flip-flop clock. The flip-flop controls the run/pause state of the circuit, so its output gates the 100 Hz clock into the first (hundredths of a second digit) counter.

The reset button doesn't need a flip-flop. It just needs to generate a pulse that feeds the MR inputs of all the counters. For the tens-of-seconds counter, an MR pulse is also needed when the count reaches 0110b as I explained earlier; you need to gate the reset button pulse with the output of the AND gate that detects 0110b and feed the gate output into the MR input for that counter.

Oh like a Jfet gates? I think I might have been getting mixed up with logic gates. So reset would essentially be a NO debounced switch attached to each chips MR. For the AND gate, why do I need a pulse at all?

 

[KrisBlueNZ]

I was talking about logic gates, not JFET gates.

You need a logic gate of some kind to generate the MR signal for the tens of seconds counter. It needs to combine your global reset pulse (from the Reset button after debouncing) with the output of the logic gate that detects when bits 1 and 2 of that counter are both high. Assuming you use all positive logic (i.e. logic high means signal is active), the gate that detects bits 1 and 2 high will be an AND gate, and the gate that combines the AND gate's output with the debounced Reset pushbutton signal to provide the MR signal to the tens of seconds digit counter needs to be an OR gate. You can't get a single IC with an AND gate and an OR gate but you can use a trick called De Morgan's transformations to get the same behaviour with three NAND gates so you can use a single IC, a CD4011, for that gating. It's best to work out all the logic you need in your circuit first, then figure out how best to split it up into gate ICs. De Morgan's transformations can reduce the number of different gate ICs you need.

You're right that you don't need a pulse from the AND gate that detects a count of 0110. As soon as that count is detected, that chip's MR input should be asserted. That will clear the count immediately, so the outputs will all go low and the AND gate output will go low too. This will generate a pulse of the right length to clear the counter. You don't need any external pulse generating circuit.

 

[blures]

I was talking about logic gates, not JFET gates.

You need a logic gate of some kind to generate the MR signal for the tens of seconds counter. It needs to combine your global reset pulse (from the Reset button after debouncing) with the output of the logic gate that detects when bits 1 and 2 of that counter are both high. Assuming you use all positive logic (i.e. logic high means signal is active), the gate that detects bits 1 and 2 high will be an AND gate, and the gate that combines the AND gate's output with the debounced Reset pushbutton signal to provide the MR signal to the tens of seconds digit counter needs to be an OR gate. You can't get a single IC with an AND gate and an OR gate but you can use a trick called De Morgan's transformations to get the same behaviour with three NAND gates so you can use a single IC, a CD4011, for that gating. It's best to work out all the logic you need in your circuit first, then figure out how best to split it up into gate ICs. De Morgan's transformations can reduce the number of different gate ICs you need.

You're right that you don't need a pulse from the AND gate that detects a count of 0110. As soon as that count is detected, that chip's MR input should be asserted. That will clear the count immediately, so the outputs will all go low and the AND gate output will go low too. This will generate a pulse of the right length to clear the counter. You don't need any external pulse generating circuit.

Doesn't the reset switch to toogle between high and low as well? What I mean is how do you make it wait to count after you hit the reset button until you hit start?

 

[blures]

Am I making an AnD gate with the 555 and the jk flip flop?

 

[KrisBlueNZ]

You need the reset button to reset the run/pause flip-flop. Both the D-type and the JK-type flip-flops have Set and Reset inputs.

No! You don't need a 555 at all.

I'll draw up a schematic. That will save time for both of us.

 

[BobK]

I think the '555 is his clock.

Bob

 

[blures]

Yes I am going to use the 555 as my clock. And then I put it into an AND gate with the output of my JK flip flop. I have a debounced switch normally open going to +5v as my clock pulse for the JK. So when I push the button, output of the the jk is HIGH and I my clock pulse will be able to pass through my AND gate as normal (the output of the AND gate is connected to the clock pulse of my counter). Push the button again and the now none of my 555 pulse will get through.Because of the toggle on and off. This was what I thought you meant. Would this not work?
I would love to see a schematic of what you we were thinking.

 

[KrisBlueNZ]

Yes, that's the idea. The question you asked was whether you would be "_making_ an AND gate _with_ the 555 and the JK flip-flop". So I answered no. You need to AND the output of the 555 with the JK flip-flop.

I'm working on the schematic now. It will take a little while.

 

[KrisBlueNZ]

OK, here's the design I've come up with.

Here's a circuit description.

U1A debounces SW1, the RUN/PAUSE pushbutton. Its output goes high while the button is being pressed. This signal clocks U3A which is wired as a toggle flip-flop. It controls whether the circuit counts or not, by controlling the gating of the 100 Hz clock in U2B.

U1B debounces SW2, the RESET pushbutton, and provides a pulse at reset. Its output is named +CLEAR and it clears all the counters and resets U3A, so counting stops when the circuit is reset.

U4 implements a crystal-controlled oscillator that runs at 32000 Hz as set by X1. This frequency is divided by cascaded divide-by-two stages implemented as toggle flip-flops. When the count in the flip-flop array reaches 10100000 binary (Q7 and Q5 high), U1C's output goes low and U1D's output goes high, resetting the count immediately. This causes U4 to divide by 160 (128+32), producing an output frequency of 200 Hz on its Q7 output, which is divided by U3B, also wired as a toggle flip-flop, to give a 100 Hz squarewave with exactly 50% duty cycle.

The 100 Hz clock must have a 50% duty cycle for consistent timing measurement, because it is gated with the RUN signal which changes asynchronously according to button-presses.

U5 (MC14553) implements the hundredths of seconds counter. It is clocked from the gated 100 Hz signal and is held reset when +RESET is high. The internal multiplex oscillator is disabled (pin 4 is tied low) so the device always asserts the value in its bottom digit on its four outputs. It acts as a 4-bit BCD up-counter. The MC14553 advances on falling edges on its CLK input pin.

These outputs drive U10, which contains a 4-bit decoder that translates the BCD value into an appropriate display pattern, and displays it. The LEDs and logic are both powered from the 5V VCC rail. Decimal points are not used. Blanking is not used. The internal latch is permanently set to transparent so the device constantly responds to its D0~3 inputs.

U5 operates as a decade counter. When its digit wraps from 9 to 0, a falling edge will occur on its Q3 output. This provides the clock to U6, which implements the tenths of seconds digit in the same way, and clocks U7, which implements the seconds digit in the same way, and clocks U8, which implements the tens of seconds.

The tens of seconds digit needs to count 0, 1, 2, 3, 4, 5, 0, 1, 2, ... so U8's MR (master reset) input has gating that detects when it reaches 6 (0110 binary) and immediately resets the count to zero. This does not affect the other counters, which are reset only by the +CLEAR signal.

When U8's Q1 and Q2 outputs are both high, indicating a count of 6, U2C's inputs are both high and its output goes low. This forces U2D's output high, which resets the count immediately (after the propagation delays in U8), causing U2C's output to return high and removing the reset from R8. U2D includes the +CLEAR in its gating; when +CLEAR is high (active), U2A's output goes low and this forces U2D's output high, resetting U8.

U8's Q2 output goes low when its digit wraps from 5 to 0. This signal is used as the clock to U9, the minutes digit. The stopwatch can count up to 9:59.99 then it resets to 0:00.00. At that time, there will be a falling edge on U9's Q3 output, but this output is not used (except by U14).

The whole circuit runs from 5V DC. The TIL311s require a 5V supply.

If you want to use a 555 for your timebase, delete U4 and tie the inputs of U1C and U1D low or high (doesn't matter which), and provide a 200 Hz clock into U3 pin 11.