4066 switches leaking in sample and hold circuit?

[AFex54]

ahh! so the transistor is only there to generate a negative pulse for a 555... I really should have noticed this sooner since Ive used this exact circuit before in my analogue step sequencer and also since none of differentiators schematics online featured a transistor...

well, that solves that and after removing the transistor Im now successfuly sampling BUT yet another issue has popped up, after i press a key and sample I have to wait about 5 seconds until I press a different key or the it doesnt sample the new voltage.

Im using a 5K resistor and 0.1μf cap which should equate to 0.5ms or 500μs

edit: Sunnysky, the transistor could be bad, I had to salvage it from an old circuit board

 

[Sunnysky]

can you redraw entire cct?

Q1 in this link Is actually an inverted pulse, not what is needed. https://www.electronicspoint.com/attachments/s_h-png.20729/
5 seconds ??

 

[AFex54]

can you redraw entire cct?

Q1 in this link Is actually an inverted pulse, not what is needed. https://www.electronicspoint.com/attachments/s_h-png.20729/
5 seconds ??

yes, about 5 seconds. if I press any key in that time the voltage doesnt change and the 5 second 'timer' resets, if i wait till after the 5 seconds pressing a different key will successfully sample a new voltage.

Here is the redrawn circuit, the SPST switch is the key and the potentiometer controls the 'note' i.e voltage(there are 30 in total, connected to a bus with diodes, but I just drew one keep the diagram simpler)

Im very tired and could have a made mistake when soldering, I will resume my work on it tomorrow and hopefully we can find out why the sampling is locked to 5 second intervals

 

[Sunnysky]

the pot value * C is your problem possibly , try 5k on switch out to ground.

 

[AFex54]

the pot value * C is your problem possibly , try 5k on switch out to ground.

like so?

 

[Sunnysky]

Yes this discharges, the cap to 0V on both sides, but does not alter the Pot voltage.

Not sure what the point of this circuit is.

 

[AFex54]

Yes this discharges, the cap to 0V on both sides, but does not alter the Pot voltage.

Not sure what the point of this circuit is.

Thank you, now it works perfectly!

the purpose of this is simply to maintain what ever voltage the potentiometer produces after the SPST switch is opened, the potentiometers votlage determines the musical note of a voltage controlled oscillator.

the voltage needs to be maintained because musical synthesizers feature something called 'release' which fades out the volume of a note once you let go of a key, without the sample and hold the voltage would cease as soon as I let go of a key ruining the 'release' effect.

here is a wikipedia page that explains it better than me:
https://en.wikipedia.org/wiki/Synthesizer#Attack_Decay_Sustain_Release_.28ADSR.29_envelope

 

[AFex54]

Oh actually its not so perfect, I can sample without any delay but the samples arent consistent, if press the key multiple times the voltage drifts a small random amount each time

EDIT: I figured I may aswell make a recording of it with my synthesizer since its working now.

here is the same key being pressed multiple times, you can hear the drift:
http://vocaroo.com/i/s18lTrwue62m

 

[Sunnysky]

like so? ....
I just realised i made a mistake and the capacitor value is actually 0.01uf
View attachment 28225

I assume your 9V is constant, but if not you may need to add a large cap to it.
You can try larger R values on the original 5k to see if the charge time is insufficient.

They make better analog switches with lower R values, or you can use smaller C values if feasible as well.

depending on layout, there may be some noise getting sampled that causes it to sample a ripple being either high or low, which matches the sound being random sharp or flat.
If you have long wires for this schematic, keep them short or use twisted pair or a shield or perhaps the cap on 9V will fix that near the 4066, as well add a decoupling cap on the 4066 Vss-Vdd

 

[AFex54]

I assume your 9V is constant, but if not you may need to add a large cap to it.
You can try larger R values on the original 5k to see if the charge time is insufficient.

They make better analog switches with lower R values, or you can use smaller C values if feasible as well.

depending on layout, there may be some noise getting sampled that causes it to sample a ripple being either high or low, which matches the sound being random sharp or flat.
If you have long wires for this schematic, keep them short or use twisted pair or a shield or perhaps the cap on 9V will fix that near the 4066, as well add a decoupling cap on the 4066 Vss-Vdd

Im not sure what constitutes 'constant' but the '9V' on the schematic is coming directly from a 9V mains adapter.

I changed R to 10k and C to 1μF but it didnt have any effect,

and I have added 2 decoupling caps already, a 1μf and 0.1 μf

EDIT: I tested my mains adapter with a voltameter and it hovers at 9.14V with occasional fluctuations to 9.13V and 9.15V, that seems pretty consistent to me.

 

[Sunnysky]

further debug may require a scope to isolate voltage errors.

 

[AFex54]

further debug may require a scope to isolate voltage errors.

ok, thanks for the help so far