J
JosephKK
Just the same, where is the channel? What is the orientation?
It looks to me as if:
- The drain is along the bottom of the device... looks like an unbroken
plane.
- There's a gate metallization layer, which then dives down through
multiple vias to create a set of gate regions, each of which forms
the perimeter of a hexagon
- Each channel is an upright, hexagonal cylinder of silicon
(appropriately doped) leading from the drain upwards, surrounded
by the gate region
- The source metallization, along the top, contacts the upper
portion of the hexagonal channel.
This basic structure of a hexagonal vertical channel is then tiled
across the horizontal plane of the device.
Current flows horizontally through the metallization layers, and flows
vertically through the pattern of channels.[/QUOTE]
That does not match the device physics. Most bulk flows are vertical,
channel flows are horizontal. Carefully consider where and how the
gate voltage creates the inversion channel to allow conduction and
what the spatial orientation of the carrier flows are through the
inverted channel region. Compare to simple MOS enhancement mode
structures as needed.