What's the best bypass caps?

[Active8]

[snip]

DOS lives!

yeah, but Linux Rules!

 

[Ian Buckner]

Hi John,

Just so you know, the core can (and does) suck 2.5A for a very short
period of time. Just after the download is complete, as it sets all
of the flops into their initial state.

This <http://www.xilinx.com/xapp/xapp189.pdf> may seem like overkill,
but if that 2.5A spike causes the voltage to droop enough, the chip
will reset back to its uninialized state.

Gary
g w helbig -at- yahoo -dot- com

It is not just a turn-on spike. We have designs that take in excess of
5A continuously for the core. If you care about jitter or skew, or
making
sure your design does not have odd, occasional, impossible to find
errors, you do need to be _very_ careful about decoupling.

There are a number of papers on the web on decoupling schemes,
from companies dealing with high speed CMOS (processors etc),
which advocate using a range of values so that the series resonances
extend over a wide range of frequencies (I only have these in pdf
format, no url's). You can measure the effectiveness of your
decoupling using a network analyser.

Regards
Ian

 

[John Larkin]

It seems a little odd, quoting metric dimensions when the imperial
part size is quoted. This is not necessary.

For clarity -

1210 is ~ .120 x .100 (metric part sixe is 3225 ~ 3.2 x 2.5mm)
1206 is ~ .120 x .060 (metric part size is 3216 ~ 3.2 x 1.6mm)
0805 is ~ .080 x .050 (metric part size is 2012 ~ 2.0 x 1.2mm)
0604 is ~ .060 x .040 (metric part size is 1608 ~ 1.6 x 0.8mm)
0402 is ~ .040 x .020 (metric part size is 1005 ~ 1.0 x 0.5mm)
0201 is ~ .020 x .010 (metric part size is 0603 ~ 0.6 x 0.3mm)

Do we see a useful pattern here?

Anything smaller than 0805 - check with fab house for their ability to
handle parts automatically. There may be penalties, due to tape and
reel incompatability (like trashing every second part on the tape).

Cost, performance and real estate benefits below 0604 may not be
naturally occuring either. This is particularly the case on .060 FR4.
Anyone care to guess why this is the case?

Check first.

RL

If you like reference designators, and we do, the smallest ones you
can screen are as big as an 0603.

John

 

[Richard]

who's got insertion heads small enough that
they won't trash adjacent parts?

That's an interesting point... how much KeepOut is normally required
around a chip cap/resistor for the placement equipment? How much does
it vary with the size of the chip?

 

[Andrew Paule]

Bypass caps are a large issue, but what you need to concern yourself
with is ESR and ESL - you need to ba able to sink/supply enough current
for transitions . This means that the whole system must be examined -
from pad type/via size,plating,placement (I like em as close as possible
to cancel mutual inductance), depth to plane layers, etc. I think that
most of us have gotten by with some tricks that we learned in the past,
but as edge rates rise (along with pins switching), we are going to have
to take a long hard look at these things. I recommend doing some
simulations with a good tool before you make any quick judgements -
placment, size, stackup, Cu plating, vias, ESR/ESL of part, etc. I've
worked in a world where 1ns was slow rise, and bypass became a huge
issue. It will become a huge issue in digital design - it's not the
clock of the system but the rise/fall time of the ouputs and impedance
control that are the real issue.

Andrew

Bill Sloman wrote:

The multilayer 0.1uF 0805 parts witn X7R dielectric have an impedance
minimum at of the order of 100MHz, and - back in 1989 - we had an
object lesson in what this means at 800MHz. One of my guys didn't
really believe the application notes for the Gigabit Logic GaAs parts,
and skipped the (1810) 1nF porcelain dielectric microwave capacitor
(good to about a GHz) [...]

Both of these caps then seem to have about 25pH of ESL, which
doesn't sound credible.

We didn't have the gear to measure the high frequency impedances, but
whatever the loss mechanism, the 100nF multilayer X7R clearly had a
much higher ESR at 800MHz. I always assumed that the dielectric was
the problem rather than the inductance of the connections. American
Technical Ceramics made a great deal of fuss about the porcelain
dielectric in thier microwave capacitors.

The way you mount them is more important
than the properties of the caps themselves.

We mostly mounted them on the under-side of the board, on the opposite
side to the surface-mount parts we were decoupling. At least four of
the inner layers of the board were devoted to various power planes -
it went component(IC) side, -2V, -5.2V, +5V/-3.4V, 0V and track
(decoupling caps) side.

The -3.4V was for the GaAs logic which was not mixed in with the TTL
parts, so that ground plane split pretty naturally.

The via's went straight to the relevant power planes, and were offset
from the lands for the IC leads and the capacitor contacts - IIRR the
boards came with the vias filled with solder and covered with
solder-mask.

(How *did* you
mount them then? 25pH of ESL would be quite a trick! A simple via
between opposite sides of a standard 1.6mm PCB is ten times that!)

I measured the ESL of a bunch of capacitors some time back.
A 1206 ceramic standing upright on a ground plane measures
about 900pH. I'd expect about the same for an 1810 component,
since it's both 50% longer and wider. ESL does not depend
on capacitance, nor on dielectric. It's all in the geometry
of the part and its surroundings.

Once you have a 100nF ceramic chip capacitor as bypass, there
is no advantage in adding smaller-valued similarly shaped caps
for HF.

That wasn't our experience - my colleague (technically my project
leader at the time, though he didn't take his status all that
seriously) shared your opinion, encouraged by a rather cramped layout,
and had to recant.

On the other hand, some manufacturers make, e.g., *0612*
parts, that is, they're short and wide. Syfer comes to mind.
That *does* help. (Their web site sucks, though :-( )

Sounds like a good idea. Back in 1989, we got what we could from the
microwave suppliers.

 

[Spehro Pefhany]

If you like reference designators, and we do, the smallest ones you
can screen are as big as an 0603.

But, things like cellphones don't have them any more. Just
wall-to-wall itty-bitty parts.

What do you mean, RL? Why is the board thickness a factor? Minimum via
size for PTH?

Best regards,
Spehro Pefhany

 

[Paul Burridge]

yeah, small. depends on what you can get away with and what you're
bypassing. i'd look to shoot for a fractional ohm like .1 - .2, but i
won't say it's written in stone. figure that 10A rf current through .1
ohm is 1V! what's that 1V in relation to the rest of the network and
will it be a problem? the other consideration is the information carried
by the RF. audio is a much lower freq and you'd want that bypassed with
a big cap. the reason you see small caps in parallel with those big boys
is because the small ceramic jobs have lower ESR and ESL than the
electrolytics. you don't want an rf voltage developing across the big
cap.

This is probably a stoopid question, but is any bypassing required for
a 555 IC in free running oscillator configuration if the frequency of
operation is less than a few hundred hertz?

 

[Bill Sloman]

Bypass caps are a large issue, but what you need to concern yourself
with is ESR and ESL - you need to ba able to sink/supply enough current
for transitions . This means that the whole system must be examined -
from pad type/via size,plating,placement (I like em as close as possible
to cancel mutual inductance), depth to plane layers, etc. I think that
most of us have gotten by with some tricks that we learned in the past,
but as edge rates rise (along with pins switching), we are going to have
to take a long hard look at these things. I recommend doing some
simulations with a good tool before you make any quick judgements -
placment, size, stackup, Cu plating, vias, ESR/ESL of part, etc.

Simulation is only worthwhile when you can validate it against
measurments on a more or less representative example of real-world
construction.

Jeroen Bellman and I report two different experiences with 0.1uF
surface mount multilayer ceramic capacitors - his measured ESL's
suggested that they should have been fine for decoupling 800MHz, and
our experience, back in 1989 (and probably with different 0.1uF SMD
caps) was that they were pretty much useless.

With that sort of conflict between measurements, the chances of your
simulation being off the mark are probably quite high.

I've worked in a world where 1ns was slow rise, and bypass became a huge
issue. It will become a huge issue in digital design - it's not the
clock of the system but the rise/fall time of the ouputs and impedance
control that are the real issue.

We were using Gigabit Logic's GaAs parts to generate pulse widths down
to 400psec (FWHM) - coarse pulse positioning to 1.25nsec from the
800MHz clock, and fine positioning within clock cycles to 10psec (in
theory, about 60psec in practice due to jitter on the 800MHz clock)
with a ramp/comparator stage.

 

[R.Legg]

But, things like cellphones don't have them any more. Just
wall-to-wall itty-bitty parts.

What do you mean, RL? Why is the board thickness a factor? Minimum via
size for PTH?

Distance to the via (even plugged micro-vias),and length of the via,
through to the ground plane, begin to dominate a part position's
self-resonance.

Part designators are best migrated to accompanying documentation when
SMD is really used to it's best advantage for purposes of
miniaturization.

Though the designators are not silk-screened, solder paste still is.
The paste surface tension defines the ultimate position of the part in
reflow, and any bridging kills this effect. If you've got a hundred of
them, it's still got to work every time, or the cost benefit of
automation is lost.

RL

 

[John Devereux]

This is probably a stoopid question, but is any bypassing required for
a 555 IC in free running oscillator configuration if the frequency of
operation is less than a few hundred hertz?

Yes, you should have some bypassing somewhere. Some variants of 555's (the CMOS ones
IIRC) take big current spikes during the output transition.

 

[Ian Buckner]

Hi Bill -

Unless you have good simulation/practice/validation correlation. I
worked at Wavecrest for a while, and before that Teradyne. Wavecrest
had products that were used to measure the jitter in 3+ GHz parts(~400fs
jitter on our clock source), and we aslo built 10G amps. I built systems
with rise times in the 40ps range, and simulation was required for any
foray into these things - cutting traces with an x-acto knife got
tedious. I agree that a 0.1uF cap is not going to do anything in a
400ps rise time situation (it's the rise/fall times that actually get
you), and at 1+GHz you should start looking into cap models - I learned
to like ADS and MatLab - model building is the only way to go. It takes
time and effort, but the rewards are boards that work. Package
parasitics, board parasitics, etc kill when you start going in this
range - a resistor is not just a resitor, and a cap is not just a cap.

There are caps made just for this type of decoup, microwave jobs (ATC
was good), and they supply valid s params for easy model building.

Andrew

Taking your point about rise time, I measured the transitions for
a Xilinx Virtex II part at the far end of the PCB trace at less than
500psec. Transitions at or in the chip will be faster. This was for
an LVDS pair, the 3.3V outputs are a little slower but still sub nsec.

Regards
Ian

 

[Bill Sloman]

Hi Bill -

Unless you have good simulation/practice/validation correlation.

That is what I was saying.

I worked at Wavecrest for a while, and before that Teradyne. Wavecrest
had products that were used to measure the jitter in 3+ GHz parts(~400fs
jitter on our clock source), and we also built 10G amps.

About an order of magnitude better than we were doing back in 1989 -
which is pretty much as it should be. The 60psec jitter on our 800MHz
clock was way less than state of the art even then - if I could have
got my hands on an 800MHz SAW element we would have done a lot better,
but we ended up using a
Z-Com VCO in a phase-locked loop which locked it to a 50MHz crystal
oscillator.

On the other hand, with a minimum pulse-width and time resolution of
400psec, 60psec was good enough, and certainly not bad enough to
persuade management to pay for a production batch of 800MHz SAW parts.

I built systems with rise times in the 40ps range, and simulation was
required for any foray into these things - cutting traces with an x-acto
knife got tedious.

Back in 1989 we were limited to HiLo as a digital simulator (which
turned out to be quite useful, if used with some attention to detail)
and Number One System's computerised Smith Chart. When Cambridge
Instruments upgraded their CAE a few years later, they couldn't afford
Analog Workbench, which was a bit frustrating.

I agree that a 0.1uF cap is not going to do anything in a
400ps rise time situation (it's the rise/fall times that actually get
you), and at 1+GHz you should start looking into cap models - I learned
to like ADS and MatLab - model building is the only way to go. It takes
time and effort, but the rewards are boards that work. Package
parasitics, board parasitics, etc kill when you start going in this
range - a resistor is not just a resistor, and a cap is not just a cap.

There are caps made just for this type of decoup, microwave jobs (ATC
was good), and they supply valid s params for easy model building.

The American Technical Ceramics parts that we used didn't feature
Spice models on the data sheet - that would have been a real luxury.

 

[Active8]

[snip]

There are caps made just for this type of decoup, microwave jobs (ATC
was good), and they supply valid s params for easy model building.

Andrew

ATC... duly noted.

do you know of any other parts like this with s params? i recently took
a sales call from a uWave passive supplier and would like to load my
guns before i jump into something. i'd prefer to go with something you
all have experience with rather than taking a shot in the dark based on
a uWave Journal ad.

thanks and brs,
mike

 

[Active8]

What would be scairy would be something like a CPU that needs 1.2
volts at 100 amps, goes from sleep to full-blast in nanoseconds, and
is very picky about margins.

John

the kiss approach would be to have a chump CPU to handle the fast wake-
up while the big dog rolls his/her butt out of bed.

mike

 

[Active8]

This is probably a stoopid question, but is any bypassing required for
a 555 IC in free running oscillator configuration if the frequency of
operation is less than a few hundred hertz?

bypass... bypass what?

decoupling, maybe.

better safe than sorry. if all you want is an egg timer i wouldn't worry
about it. as much as i hate to over specify, i won't say no. personally,
if i was worried about it, i'd figure out whether it could mess things
up. look at the internal circuitry of your 555s. look at the current
path from the output through the load and back to the output - a
complete loop. the 555 will need to supply current to drive that load,
the amount of which depends on the load - capacitive loads being the big
prick. if 1000 555s switch states at the same time, the power supply
filter MAY be sufficient to deal with it, but if they switch at random
rates it MAY look like many transitions closely spaced in time just
like high speed digital which won't be a good thing without individual
555 bypasses. a cumulative effect.

now i have questions for you.

has this bot competed before?

does it respond to your commands?

can you maneuver and hit the "kill the other bot" button at the same
time with positive results?

if yes, what are you worried about? i hope you're just curious about
what might go wrong and if you have no experience/confidence competing
this bot, i don't blame you.

OTOH, if this bugger responds to commands reliably already, please,
let's start talking about killing other bots. i want to know what we can
do to humiliate Jay Leno one day >-) not that he can't/hasn't be/been
beaten to crap (don't know - i figure he can/has pay/paid for success...
media hogwash, y'know?)

let's talk maximum energy delivered to the load with best possible
efficiency. that's what it's about these days. laptops, bots, anything
portable running off batts. i know there's enough know how in this ng to
get the job done. let's get on with it. flip him ass over tea kettle
onto the kill blade. upper cut to the chump chin and his ass is yours.

best of luck. i'm in your corner.
mike

 

[Spehro Pefhany]

you ARE recalling correctly. those CMOS FETs take a charging current.

I recall just the opposite, that the bipolar version crowbars the
supply during switching. Let's find out..

This Philips datsheet for the (bipolar) NE555 seems to confirm that:

http://www.web-ee.com/primers/files/555AN.pdf

Due to the nature of the output structure, a high power totem-pole
design, the output of the timer can exhibit large current spikes on
the supply line. Bypassing is necessary to eliminate this phenomenon.
A capacitor across the VCC and ground, directly across the device, is
necessary and ideal. The size of a capacitor will depend on the
specific application. Values of capacitance from 0.01uF to 10uF are
not uncommon, but note that the bypass capacitor would be as close to
the device as physically possible.

And this National data sheet for a CMOS version:

http://cache.national.com/ds/LM/LMC555.pdf

The LMC555 offers the same capability of generating accurate time
delays and frequencies as the LM555 but with much lower power
dissipation and supply current spikes.


Best regards,
Spehro Pefhany

 

[John Larkin]

I think Dilabs (dielectric laboratories) has s params, but you might
have to contact them, and I know temec has them too. The dilabs site is
a good tool - they have a cap cad program that shows effect of how a cap
is structured etc. The other big thing here is mounting and pad
geometry/launch geometry. You can get ansoft or ADS to turn out some
good simulations for combos here. Much better than sitting with an x
acto and a network analyzer and screwing up a dozen boards before you
figure things out.

X-acto knives are a lot cheaper than e-m simulators!

In higher frequency arenas, I think that vendors should get you
something that fits in your modeling/simulation programs, I like s
params because they're easy (I had em explained to me by an old RF guy -
younger than me actually, but all he'd done was RF tuning).

I've tested some of the dilabs parts that were advertised as super
wideband DC blocks. I suspect they tested them on high-K substrates
where the microstrip widths were perfect matches for the size of the
part. But when a trace is wider than the cap, things aren't as nice,
and the super dilabs thing wasn't any better than a cheap 0805 cap.

To DC block on a wide trace, several small caps broadside work well.
Even better, make a z-cut and bridge that with caps. By implication, a
bypass can be trashed in extreme situations by its pad geometry. But I
guess we all knew that.

But I digress. Maybe I need coffee. Maybe I'll go to Wescon. Anybody
been there this year? Is it worth it? Wescon used to be great, with
all the biggies there in force, but has declined to a cheap components
show, mostly.

John

 

[Andrew Paule]

I dunno - 1 seat for Matlab and ADS is about 35K - I amortize
engineering time (I owned my own company and got some accounting
practice there) at about 1K per day - how many days does it take for
this, plus then you have other things you can do with the tools. I've
seen (more than once, done it myself) 4 or 5 engineers trying to figure
things out for a week on what turns out to be a launch geometry on a pad
away from what we thought was critical -a computer can iterate much
faster than I can. Yes, an x-acto is cheaper, but so is tape and mylar
for laying out boards - reason that most big companies and many smaller
ones spring for good tools is economic in the long run - short term
solutions and thinking are not good. I agree that blocking caps on a
mismatched trace/launch suck - I try to get a stack/line width combo
done for critical lines that allow you to launch easily. Work with your
board vendor - they've got a stake in it, and getting people to work
with each other is much better in the long run.

I think that most shows are going to be in the boat - I was the last of
my group to go at my previous place of employment (6 rounds of layoffs),
and companies are not yet starting to buy capital equipment - ATE
suppliers are struggling (can you say some are down more than 90%), and
with show costs as high as they are........ mostly what you'll see are
component manufacturers.

Andrew

 

[Active8]

[snip]

Jay Leno's into this? Perhaps I'll see him at the World Championships
at the end of the month; they're being filmed within the same schedule
at the same location in Britain. I can't say I particularly like the
guy myself!

he's on Battle Bots here on tv. i haven't watched it in a while, but i
think he flaps his gums over the PA system while someone else drives.
totally annoying. his bot is Chin Killa - named after that chin
protruding from his ugly mug. I NEVER liked him.

br,
mike

 

[Paul Burridge]

he's on Battle Bots here on tv. i haven't watched it in a while, but i
think he flaps his gums over the PA system while someone else drives.
totally annoying. his bot is Chin Killa - named after that chin
protruding from his ugly mug.

I think that's regarded as a very masculine trait. Wimmin are supposed
to go for guys like that as they're like alpha male-types and
therefore more likely to dominate other males, win food and such like.
Well, that's wimmin for you. :-|

I NEVER liked him.

Does anyone?