Very low frequency 100 microvolt/sec triangle ramp with adjustable limits and slope

[Steve]

I'm looking for a design (analog ?) for a triangle ramp generator with
an adjustable slope around 100 microvolts / sec. Its output voltage
ramp limits need to be independtly adjustable. The typical range is
2.0 to 4.8 volts which results in a total period of 15.6 hours. It
would need to be able to be reset or held at one of its limits (its
lower voltage) and started upon an external signal (relay contact
closure, digital logic state change, etc). Unipolar positive output
voltage range is fine.

 

[Steve]

A 24-bit sigma-delta D/A converter from Burr-Brown (now part of TI)
turned out to be pretty attractive; for the slow rates I was planning

looks like 20 bits is the best they do now (DAC1220)

 

[Joerg]

I'm looking for a design (analog ?) for a triangle ramp generator with
an adjustable slope around 100 microvolts / sec. Its output voltage
ramp limits need to be independtly adjustable. The typical range is
2.0 to 4.8 volts which results in a total period of 15.6 hours. It
would need to be able to be reset or held at one of its limits (its
lower voltage) and started upon an external signal (relay contact
closure, digital logic state change, etc). Unipolar positive output
voltage range is fine.

Can you use the timer of a uC and PWM a reference that is accurate
enough for your purpose? Maybe even the old TL431 suffices

Then lowpass it via RC.

 

[Uwe Hercksen]

I'm looking for a design (analog ?) for a triangle ramp generator with
an adjustable slope around 100 microvolts / sec. Its output voltage
ramp limits need to be independtly adjustable. The typical range is
2.0 to 4.8 volts which results in a total period of 15.6 hours.

Hello,

I would prefer a digital solution for such long periods. With Direct
Digital Synthesis (DDS) it is no problem to generate periodic signals
with frequencies of Millihertz, Mikrohertz and even Pikohertz.
http://www.analog.com/en/rfif-components/direct-digital-synthesis-dds/products/index.html

But for http://www.analog.com/static/imported-files/data_sheets/AD9830.pdf
the minimum clock frequency given in the diagrams is 10 MHz, maximum 50
MHz and the accumulator is 32 Bits long. Both limits the minimum
possible frequency. But with a DDS Chip for slower clocks and with a
larger accumulator very small frequencies should be possible. When only
very small frequencies are needed, the DDS may be programmed using a
suitable mikroprozessor. An internal bit width of 32 or 64 bits would be
helpful, but support for very long integers spread over multiple words
would do it too. Don't try using double precision floating point values
for DDS, long integers are needed. Some counters for the generation of a
slow clock for the DDS algorithm are also needed.

Bye

 

[Uwe Hercksen]

Can you use the timer of a uC and PWM a reference that is accurate
enough for your purpose? Maybe even the old TL431 suffices

Then lowpass it via RC.

Hello,

the necessary very large time constants for the lowpass filter might be
a problem when a period time of 15,6 hours is needed.

Bye

 

[Rene Tschaggelar]

Hello,

I would prefer a digital solution for such long periods. With Direct
Digital Synthesis (DDS) it is no problem to generate periodic signals
with frequencies of Millihertz, Mikrohertz and even Pikohertz.
http://www.analog.com/en/rfif-components/direct-digital-synthesis-dds/products/index.html


But for http://www.analog.com/static/imported-files/data_sheets/AD9830.pdf
the minimum clock frequency given in the diagrams is 10 MHz, maximum 50
MHz and the accumulator is 32 Bits long. Both limits the minimum
possible frequency. But with a DDS Chip for slower clocks and with a
larger accumulator very small frequencies should be possible. When only
very small frequencies are needed, the DDS may be programmed using a
suitable mikroprozessor. An internal bit width of 32 or 64 bits would be
helpful, but support for very long integers spread over multiple words
would do it too. Don't try using double precision floating point values
for DDS, long integers are needed. Some counters for the generation of a
slow clock for the DDS algorithm are also needed.

Bye

Since the required output is only a triangle,
no sine, a CPLD could be used as timing circuit.

Rene

 

[Uwe Hercksen]

I'm looking for a design (analog ?) for a triangle ramp generator with
an adjustable slope around 100 microvolts / sec. Its output voltage
ramp limits need to be independtly adjustable. The typical range is
2.0 to 4.8 volts which results in a total period of 15.6 hours. It
would need to be able to be reset or held at one of its limits (its
lower voltage) and started upon an external signal (relay contact
closure, digital logic state change, etc). Unipolar positive output
voltage range is fine.

Hello,

a DAC with 16 bit resolution allows steps of less than 100 microvolt for
a unipolar maximum voltage of 5 V. 18 or 20 bits will be even better.

The triangle ramps with adjustable slopes togehter with reset, hold and
start may be programmed using a mikroprozessor. Care should be taken
when implementing the slow slopes, the use of single precision floating
point values is not sufficient for very small slopes and frequent
updates several times a second. If you add to the single precision
floating point representation of 4 volts less than 59 nanovolts, the
result is still 4 volts.
The full implentation of DDS is not necessary if the resolution of the
frequency dividers by the timers of the mikroprozessor is small enough.

An analog solution would be very difficult, the time constants of
several hours realized with resistors and capacitors will not be stable.

Bye

 

[Ban]

Hello,

a DAC with 16 bit resolution allows steps of less than 100 microvolt for a
unipolar maximum voltage of 5 V. 18 or 20 bits will be even better.

The triangle ramps with adjustable slopes togehter with reset, hold and
start may be programmed using a mikroprozessor. Care should be taken when
implementing the slow slopes, the use of single precision floating point
values is not sufficient for very small slopes and frequent updates
several times a second. If you add to the single precision floating point
representation of 4 volts less than 59 nanovolts, the result is still 4
volts.
The full implentation of DDS is not necessary if the resolution of the
frequency dividers by the timers of the mikroprozessor is small enough.

An analog solution would be very difficult, the time constants of several
hours realized with resistors and capacitors will not be stable.

Bye

If you want to do this in analogue, you might do your own D/A converter with
a charge amplifier with a big capacitor say 10uF and a low bias current
opamp say AD845.
You can then transfer little bits of charge with a 100p cap and switches
driven from a sqarewave generator. Each time the output will rise in the
proportion of the caps times the voltage you charged the small cap. So each
step is i.e. 5V/100000= 50uV. The switch is critical, LT has something like
a flying cap switch (forgot the number), since its dual the charge injection
is cancelled. The principle is shown below. To subtract you use a neg
reference or another pair of switches.

.----. 10u ||
| | -----o--------||----.
| | | | || |
=== o /o | |
GND / | |
/ | |\ |
o '----|-\ |
| | >------'
100p | .--|+/
--- | |/
--- ===
| GND
o
\
Vref \
o o \o
| | |
'-----' ===
GND
(created by AACircuit v1.28.6 beta 04/19/05 www.tech-chat.de)
ciao Ban
Apricale, Italy

 

[Joerg]

Hello,

the necessary very large time constants for the lowpass filter might be
a problem when a period time of 15,6 hours is needed.

Well, you don't have to run the PWM at "turtle speed"

All you need to do is have the PWM run at the max frequency the timer
can do while still being long enough for the accuracy, and then lowpass
enough to muffle the resulting ripple so you get under 20bits or
whatever is needed. It has nothing to do with the 15.6h total, all you
are building is a "poor man's DAC".

Of course the reference might need to be rather accurate but Steve
hasn't said anything about his requirements there. That would go for any
solution though, something needs to provide a baseline reference.

 

[Joerg]

If you want to do this in analogue, you might do your own D/A converter with
a charge amplifier with a big capacitor say 10uF and a low bias current
opamp say AD845.
You can then transfer little bits of charge with a 100p cap and switches
driven from a sqarewave generator. Each time the output will rise in the
proportion of the caps times the voltage you charged the small cap. So each
step is i.e. 5V/100000= 50uV. The switch is critical, LT has something like
a flying cap switch (forgot the number), since its dual the charge injection
is cancelled. The principle is shown below. To subtract you use a neg
reference or another pair of switches.

.----. 10u ||
| | -----o--------||----.
| | | | || |
=== o /o | |
GND / | |
/ | |\ |
o '----|-\ |
| | >------'
100p | .--|+/
--- | |/
--- ===
| GND
o
\
Vref \
o o \o
| | |
'-----' ===
GND
(created by AACircuit v1.28.6 beta 04/19/05 www.tech-chat.de)
ciao Ban
Apricale, Italy

Have you thought about the leakage currents of the 10uF cap and the
board? You'd almost have to run this in a vacuum. Or pack it all into a
thick layer of lacquer.

 

[Ban]

Have you thought about the leakage currents of the 10uF cap and the board?
You'd almost have to run this in a vacuum. Or pack it all into a thick
layer of lacquer.

Of course you need a good film cap, I didn't look up data sheets for caps,
what is the typical leakeage there? Somebody in this group measured caps
some years ago and they were keeping the charge very well.
If you use pdip ICs you can bend up the sensitive pins, also this node is on
virtual earth.
I responded here, because nobody was encouraging an analog solution.
Also the OP didn't specify any specs, so why not?
Ban

 

[Joerg]

Of course you need a good film cap, I didn't look up data sheets for caps,
what is the typical leakeage there? Somebody in this group measured caps
some years ago and they were keeping the charge very well.

They do but only if they are really tucked away and cut off from the
environment (moisture, pollution and so on). The datasheets usually
state several tera-ohms for the more expensive caps:

http://www.epcos.com/inf/20/20/db/fc_05/MKT_B32591_94.pdf

I found that in reality they aren't quite as great. Analog slopes longer
than 10 minutes are usually a royal pain.

If you use pdip ICs you can bend up the sensitive pins, also this node is on
virtual earth.

Yes, you can do a lot with guard rings and so on. But again, you'd
almost have to encapsulate the whole thing.

I responded here, because nobody was encouraging an analog solution.
Also the OP didn't specify any specs, so why not?

Naturally I am all for analog because that's my bread and butter. But to
be honest, I would PWM this one.

 

[Steve]

Yes, it does seem that digital would be best for me. This design will
also be measuring current during the voltage scan using a computer
data acquisition card, so a card with a dac could be used to generate
the ramp. But the less expensive 16 bit dac cards do not allow their
reference and offset voltages to be set externally, so their range is
restricted to +/- 10 V which is 0.3 mV lsb. In practice, that may be
ok.

 

[Joerg]

Yes, it does seem that digital would be best for me. This design will
also be measuring current during the voltage scan using a computer
data acquisition card, so a card with a dac could be used to generate
the ramp. But the less expensive 16 bit dac cards do not allow their
reference and offset voltages to be set externally, so their range is
restricted to +/- 10 V which is 0.3 mV lsb. In practice, that may be
ok.

That could work. Use several of the 16-bit outputs and sum them into a
node. Set the resistor to ground so that full scale covers 4.8V. You can
add in an offset to get the -10V to 2V for even better granularity.
That, plus a nice RC lowpass and you could be home

Just make sure the offset comes from the card, like from another DAC, so
you don't back-feed into the card when someone trips over the computer's
power cable.

[...]

 

[Paul Keinanen]

The micros from Silabs have built in DACs. They are only 12 bits but
that may be all you really need. You can follow the DAC with a low
pass filter and dither the LSB to make the ramp much smoother. Since
you can stuff numbers into the DAC at about 100KHz and your output
doesn't have much of a bandwidth the filter can be a very serious low
pass.

Apparently these devices use R/2R type DACs.

While in principle a high speed low resolution DAC could be used as a
slow speed high resolution DAC by oversampling, the linearity errors
could be a problem with such slow ramps.

While an ideal 12 bit converter would generate a clean step from say
7FF.00 to 800.00, the actual analog step could be 7FF.ff to 800.00 and
the device would still considered monotonic .

At least a quite large (several LSB) dither noise amplitude in the
digital domain needs to be added, to get rid of the worst linearity
errors. Some RC filtering on the analog side will then remove the
dither noise.

If you get the more "up market" ones, the micro has a fairly accurate
oscillator built in. This may save you from needing a crystal.

On delta/sigma etc. type converters the fluctuation of the clock would
alter the output value, thus an oscillator with low phase noise is
required and the oscillator should also be free of microphonics,
unless the RC filter cut-off would be below 1 Hz, however, such
filters would either have a very high output impedance or would
require a huge non-electrolytic capacitor.

Thus, high quality timing is requiring, so that the analog RC filter
would only have to remove oversampling noise, thus operating at a high
(100 Hz - 10 kHz) cut-off frequency.

 

[Steve]

I've already posted a digital scheme which will allow you to accomplish
what you said you wanted to do, but without the constraints you've
introduced which the "less expensive" DAC cards will place on you.

can you tell us what, exactly, you want to do and how much money you've
got to be able to do it with, please?

This will be scanning voltage for electrochemical compound research
for battery cycling. Slow scan needed because of slow diffusion in
the materials. University research, so money is an issue. Even
hundreds of dollars cost difference can be an issue. Looking for
in-lab built device(s) instead of spending thousands for a commercial
instrument. 12 bit DAC interface cards are $150, 16 bit are $400.

 

[Joerg]

This will be scanning voltage for electrochemical compound research
for battery cycling. Slow scan needed because of slow diffusion in
the materials. University research, so money is an issue. Even
hundreds of dollars cost difference can be an issue. Looking for
in-lab built device(s) instead of spending thousands for a commercial
instrument. 12 bit DAC interface cards are $150, 16 bit are $400.

I'd get an EE student to design, build and test it. Lots of them would
love that job, they aren't expensive, they have to learn the ropes
anyhow and when they can stuck they can ask here

 

[JosephKK]

That would be some significant time constant for the RC filter.

Yep. Even if you used high frequency dither to get a smoother average
slope out of the DAC.

 

[JosephKK]

It depends on whether you need a perfect ramp or only a monotonic rise
that is good over modest spans.


The Silabs ones appear to have a step size that is always within
about
1/4 LSB of what it should be.


The dither can be done at the update frequency of the DAC and it works
quite well. I have done it. The low pass filter needed to get a good
signal in the 0-100Hz band is not all that hard to do. The dither
doesn't need to be random. My code tends to create chaos for the
points
that are not rational values. For others it makes a fast cycle of 3
points.

Yes. More interestingly, the dither pattern can include a low value
linear slope component as well. The result is sometimes called noise
shaping.

 

[Joerg]

Yep. Even if you used high frequency dither to get a smoother average
slope out of the DAC.

Who says you can only use one DAC? Use one for coarse and another for
vernier. Oh, now I've dropped the bag'o tricks and spilled it out