Analog filtering for very low frequency signals

[Joerg]

Hi John,

(My Krohn-Hite 3342 switched, lo-pass hi-pass, lab filter goes down to
0.001Hz. Biggest caps in there seem 10uF polyprops, using discrete semis!)
regards

Weren't these hand-built and the size of a Radio Flyer cart?

Regards, Joerg

 

[Terry Given]

Jim Thompson wrote:
[snip]

My experience is primarily with (NPO) chip caps for hybrids, which is
why I utilized the "p+1" method... then you can tolerate horrible df
before it even tweaks you a dB.

...Jim Thompson

Hi Jim,

whats the "p+1" method?

Cheers
Terry

For a way to swamp out dissipation effects, look over
"StateVariableFilter(P+1).pdf" on the SED/Schematics page of my
website.

...Jim Thompson

Thanks. nice.

Cheers
Terry

 

[Jim Thompson]

Hi John,

Weren't these hand-built and the size of a Radio Flyer cart?

Regards, Joerg

Careful there, Joerg, you're showing your age ;-)

...Jim Thompson

 

[Ban]

"...only..."?? Not so.

Well, with a bandwidth 500 times the center frequency you will be much more
flexible with separate filters, it might be done with a bandpass design, but
there will be no advantage.

[snip]

Sallen-Key is indeed the most suitable
topology, but keep resistors low and (unfortunately) capacitors high.

[snip]

Sallen-Key sucks... why do you declare it "most suitable topology"?

You only need 1opamp per filter, which is favourable when the opamp costs
several $$. The size of the caps will be the same with all topologies, exept
when you use a capacitor multiplier, in which case it is favourable when
they are grounded. Since the poles are not to be adjusted, S-K should be
perfectly OK. He asked for higher performance, which I translated into "less
noise".

 

[Ban]

0.05 Hz is an omega of 0.3, so 1 uF and 3 megs is the ballpark RC. Or
0.33 uF and 10M. Those are perfectly happy numbers to work around a
fet opamp. Sounds easy to me.

John

John, the noise will be 100 times higher with 10M/1k design plus the popcorn
noise of the fet-opamp with 1/f corners and noise performance at least 10
times of the AD797 at 0.05Hz, where it has less than 3nV/sqrt Hz. Look also
at the peak to peak noise diagramm from 0.1 to 10Hz, the AD797 has only
40nV.

 

[Ban]

Sampling at 150Hz will make the anti-aliasing easy, and even an 8051
ought to be able to make a pretty credible filter at that sample rate.
There are some very good 24-bit Sigma-Delta ADCs that have output
sample rates that fast, and input sample rates high enough that you
anti-alias with any R and C you find kicking around on the floor.

You still need an anti-aliasing filter, though. The advantage to
doing it with digital hardware is your frequencies are set by the uP
oscillator frequency, which will be pretty darn stable.

I think the digital approach is very valid in this case, but there will be a
I/O delay higher than with an analog filter. This might have to be
considered depending on the application. Certainly the capacitors will be
nice and small for a 30Hz LP compared to a 0.05Hz HP. But you will need
quite a high order filter to avoid aliasing. Maybe the signal is already
band limited so that will help.

 

[Tim Wescott]

Tim Wescott wrote:
- snip -

I think the digital approach is very valid in this case, but there will be a
I/O delay higher than with an analog filter.

If you use an IIR filter the system delay won't be much more than an
analog filter (the filter itself will be comparable, any excess will
just be from the acquisition and output sample time).

This might have to be
considered depending on the application. Certainly the capacitors will be
nice and small for a 30Hz LP compared to a 0.05Hz HP. But you will need
quite a high order filter to avoid aliasing. Maybe the signal is already
band limited so that will help.

The ADC I had in mind is a sigma-delta type, the AD7711 or others of
it's ilk. It samples the input signal at up to 40kHz if I read the data
sheet correctly (more if I don't), so you don't need much anti-alias on
the input. If you can't stand the aliasing products on the output
you'll need anti-aliasing there, or you need to have a digital
reconstruction filter running on the uP, which will get you out of the
8051 class fairly quickly.

 

[Tim Wescott]

BTW, I think your new paper on your web site about block diagrams in
control systems is great.

Thanks. I think very highly of that whole project, but but it's always
hard to rate one's own work.

 

[Ban]

If you use an IIR filter the system delay won't be much more than an
analog filter (the filter itself will be comparable, any excess will
just be from the acquisition and output sample time).


The ADC I had in mind is a sigma-delta type, the AD7711 or others of
it's ilk. It samples the input signal at up to 40kHz if I read the
data sheet correctly (more if I don't), so you don't need much
anti-alias on the input. If you can't stand the aliasing products on
the output you'll need anti-aliasing there, or you need to have a
digital reconstruction filter running on the uP, which will get you
out of the 8051 class fairly quickly.

Well I was referring to the before mentioned 150Hz sample rate. If you
oversample a lot more(with 40k sample 0.05Hz is almost 1/1mio!) the analog
filter gets relaxed specs, but the precision of the IIR coefficients require
more and more effort (float, double precision) so there will be an optimum
depending on your MCU/DSP.

 

[Terry Given]

"...only..."?? Not so.

Well, with a bandwidth 500 times the center frequency you will be much more
flexible with separate filters, it might be done with a bandpass design, but
there will be no advantage.

[snip]

Sallen-Key is indeed the most suitable
topology, but keep resistors low and (unfortunately) capacitors high.

[snip]

Sallen-Key sucks... why do you declare it "most suitable topology"?

You only need 1opamp per filter, which is favourable when the opamp costs
several $$. The size of the caps will be the same with all topologies, exept
when you use a capacitor multiplier, in which case it is favourable when
they are grounded. Since the poles are not to be adjusted, S-K should be
perfectly OK. He asked for higher performance, which I translated into "less
noise".

I think things are different when you have to place an IC every time you
want an opamp (interesting how quads are often cheaper than duals), then
have to place all the discretes. But S-K filters certainly are crappy
(sensitivity, etc).

I have also watched 4 different engineers (in 4 different companies) try
to build PWM filters using S-K LP topologies, only to discover that
square waves have sharp edges, and S-K filters tend to provide a direct
capacitive path from input to output, thereby ensuring that the required
opamp GBW >> that which you thought you needed..... I hereby confess to
being the first engineer I ever saw do that. I felt a lot better when I
saw others (much smarter than I) doing it - my solution was a slight
topology change (split Rin in two, with a shunt cap in the middle),
theirs was buy a much more expensive opamp. Pspice found my problem for
me (only because I looked), so I changed it before the pcb layout

Cheers
Terry

 

[Terry Given]

- snip -



If you use an IIR filter the system delay won't be much more than an
analog filter (the filter itself will be comparable, any excess will
just be from the acquisition and output sample time).



The ADC I had in mind is a sigma-delta type, the AD7711 or others of
it's ilk. It samples the input signal at up to 40kHz if I read the data
sheet correctly (more if I don't), so you don't need much anti-alias on
the input. If you can't stand the aliasing products on the output
you'll need anti-aliasing there, or you need to have a digital
reconstruction filter running on the uP, which will get you out of the
8051 class fairly quickly.

Unless you go to Cygnal, and buy the worlds most expensive 8051....

I worked on a project where they did a whole bunch of 24-bit DSP using a
25MHz single-cycle 8051 derivative beasty, that cost about $12 in volume
- I can easily buy a 32-bit whiteware DSP for less than that. The '51
derivative had stuff all ROM, so a large EEPROM was used for extra code
storage (oh god, virtual memory in an 8051, what a disaster - about 1/3
of the total code was for VM only) and it took years to get the code
reliable. Right at the outset I suggested more memory, but was assured
the larger memory parts were much more expensive. Turns out that we
could quadruple the memory for less than the price of the EEPROM, if we
leaned on the supplier a bit. oops, best not to think about the cost of
an extra 2 years code development (for a total of 16kb - not very cost
effective).

Reminds me of the programmer I once hired to develop code for a user
interface - 4x20 LDC, 5 buttons, 3 LEDs, a MODBUS interface (it was a
master). He was a smart guy, so I gave him the specs and let him rip
into it. A couple of weeks later he came and asked for more RAM - at
which point I got real concerned, the part had 2kb or so, which is
mountains! Then I found he had used 48kb of the 64kb flash to implement
a home-made (but very nice) fully multi-tasking RTOS. He wrote it all in
C, and was (automagically) using 32-bit ints as boolean flags - in an
8051, with all its bit-crunching power. No wonder he ate the RAM. I
expected it to take about 4kb of code, leaving 60kb for data. I re-wrote
the spec, explicitly specifying the data space in ROM (and RAM), and
Dave wrote a much, much, much better piece of code - about 2kb IIRC. His
previous project had been a laser printer, with 20Mb RAM, 32-bit cpu
etc, so he kinda got in the habit of gross overkill.

Cheers
Terry

 

[Ban]

I think things are different when you have to place an IC every time
you want an opamp (interesting how quads are often cheaper than
duals), then have to place all the discretes. But S-K filters
certainly are crappy (sensitivity, etc).

I have also watched 4 different engineers (in 4 different companies)
try to build PWM filters using S-K LP topologies, only to discover
that square waves have sharp edges, and S-K filters tend to provide a
direct capacitive path from input to output, thereby ensuring that
the required opamp GBW >> that which you thought you needed..... I
hereby confess to being the first engineer I ever saw do that. I felt
a lot better when I saw others (much smarter than I) doing it - my
solution was a slight topology change (split Rin in two, with a shunt
cap in the middle), theirs was buy a much more expensive opamp.
Pspice found my problem for me (only because I looked), so I changed
it before the pcb layout

You are right for high frequency S-K filters, but here we talk about 30Hz,
which is way down from 8MHz GBW of the opamp. A simple R/C post filter can
avoid this.
If you split the first R in two, you will get a 3pole filter. you can then
also increase the Q of the 2nd order filter and include the passive R/C in
front into the filter calculation. So you have a 3-pole filter at the cost
of an additional resistor and capacitor.
I have studied many topologies and I believe there are pros and cons for
every one. But given the low frequency and noise requirements S-K is one of
my favourites in this application.

 

[Terry Given]

You are right for high frequency S-K filters, but here we talk about 30Hz,
which is way down from 8MHz GBW of the opamp. A simple R/C post filter can
avoid this.
If you split the first R in two, you will get a 3pole filter. you can then
also increase the Q of the 2nd order filter and include the passive R/C in
front into the filter calculation. So you have a 3-pole filter at the cost
of an additional resistor and capacitor.

which is exactly what I did

I have studied many topologies and I believe there are pros and cons for
every one. But given the low frequency and noise requirements S-K is one of
my favourites in this application.

I like Jim's p+1 SVF. I also liked your comment re. cascaded HPF,LPF vs
a bandpass, with such a wide bandwidth. I suspect that the variance in
corner frequencies would be higher for the bandpass design, but I'd need
to check the maths to be sure.

Cheers
Terry

 

[john jardine]

Hi John,

Weren't these hand-built and the size of a Radio Flyer cart?

Regards, Joerg

Suspect that was the previous model. This is rack mount about 5" high.
0.001Hz to 100kHz, 2 identical channels of brickwall LP/HP, decade switch
settable. Magnificent piece of gear but oh so rarely used.
It's just *too* good!. The filtered signal it puts out is so enticing that
I've been drawn in and wasted time trying to approach a similar performance
using a few opamps. Totally uneconomic.
Same with power supplies. I much prefer to design and test using rubbish
PSU's. Good ones supress truths that Sods law will later reveal on site.
My experience is that lab' grade kit is great for checking out novel ideas
but a millstone if used in designing gear for customers in a real world.
regards
john

 

[Ian]

John, the noise will be 100 times higher with 10M/1k design plus the popcorn
noise of the fet-opamp with 1/f corners and noise performance at least 10
times of the AD797 at 0.05Hz, where it has less than 3nV/sqrt Hz. Look also
at the peak to peak noise diagramm from 0.1 to 10Hz, the AD797 has only
40nV.

The problem with the AD797 is that the current noise is 2pA/rtHz at 1kHz.
Using reasonable size, stable capacitors will mean that the impedance levels
are high so the current noise will probably dominate.

I did some 1/30Hz lowpass filters back in the early '70s using 1uF
polycarbonate caps (50ppm/deg C, _very_ good df/leakage as long
as you used the "sealed" versions, small, cheap) and LM308 super beta
opamps. Performance was excellent. I used a somewhat unusual topology
to get better noise, I'd have to look up what it was, it's been a while ;-)

I would suggest something like the AD8671 family rather than the AD797.
Voltage noise is higher, but the current noise is much lower at 0.3pA/rtHz.
Vp-p 0.1-10Hz is a bit higher (77nV p-p versus 50nV p-p), but that is
not what will dominate.

The suggestions to use a delta sigma ADC may be the answer, but the OP
needs to check the noise level is acceptable. For example, the AD7738
at its slowest rate with chopping enabled has a noise level of about
10uV p-p.

Regards
Ian

 

[Ken Smith]

How so? I'd suspect a polycarb or something decent would have a very
low df in the sub-Hz range.

Have you tried desinging in polycarbs lately? If you did, how did you
survive the beating you got from purchasing?

Also I've never seen them in surface mount. I haven't looked very hard,
but I think I would remember.

Numbers like 1 uF and 10 megohms seem
perfectly nice to me, with fet opamps.

That would make for quite a bit of noise. I don't know if the OP can
stand the noise in his design.

 

[Ken Smith]

Sampling at 150Hz will make the anti-aliasing easy, and even an 8051

I did something a lot like this. In my case it was about 180Hz that I
needed to measure the amplitude of. The 8051 samples at about 5KHz with
plenty of time to get around the loop.

If you like 8051s and want speed, look at the Cygnal products. 100MIPS in
an 8051 is a fun idea.

 

[Joerg]

Hi Ken,

Have you tried desinging in polycarbs lately? If you did, how did you
survive the beating you got from purchasing?

Also I've never seen them in surface mount. I haven't looked very hard,
but I think I would remember.

As an alternative the Panasonics ECH and ECH-U series is pretty good.
They are SMT but the solder process needs to be quite controlled. I only
use film caps when I absolutely have to.

That would make for quite a bit of noise. I don't know if the OP can
stand the noise in his design.

Yes. I'd go for a digital solution here.

Regards, Joerg

 

[Ken Smith]

Hi Ken,

As an alternative the Panasonics ECH and ECH-U series is pretty good.
They are SMT but the solder process needs to be quite controlled. I only
use film caps when I absolutely have to.

I've designed them in and then designed them out. Their failure rate was
the highest in the system. I was using 1% caps. A lot of them were not
1% after the board house got done. If you had to re-heat to replace one,
you had to also replace any others that are nearby. If they still worked
in the production PCB, they would fail under the normal abuse the product
was subject to.

Yes. I'd go for a digital solution here.

... or figure out a way you don't need to do it at all. This is often the
best way to solve a problem like this.

 

[Ken Smith]

Tim Wescott wrote: [...]
Well I was referring to the before mentioned 150Hz sample rate. If you
oversample a lot more(with 40k sample 0.05Hz is almost 1/1mio!) the analog
filter gets relaxed specs, but the precision of the IIR coefficients require
more and more effort (float, double precision) so there will be an optimum
depending on your MCU/DSP.

Use fixed point. If you store everything as giant integers, there is less
trouble. The 8052 has 256 bytes so you can fit nearly 32 8 byte integers
in it.