The adder is most widely used in digital system. we all are aware with full adder and parallel adder. but they give less response because of the delay. Delay pays an important role for deciding the efficiency of the circuit. now i am discussing the MUX based adder which offer less delay as compared to conventional adder. The concept of multiplexer is used to minimize the delay. Here we are discussed the verilog code of 8 bit MUx based adder.
module add8(
input [7:0] a,
input [7:0] b,
output [8:0] sum
);
wire s0;
wire c1;
wire s1;
wire c2;
wire s2;
wire c3;
wire s3;
wire c4;
wire s4;
wire c5;
wire s5;
wire c6;
wire s6;
wire s7;
wire c7;
wire carry;
assign s0 = a[0] ^ b[0];
assign c1 = ((a[0] ^ b[0]) & 1'b0 )| (a[0] & b[0]); // for select line and ? for condition statement
assign s1 = a[1] ^ b[1] ^ c1;
assign c2 = ((a[1] ^ b[1]) & c1) | (a[1] & b[1]);
assign s2 = a[2] ^ b[2] ^ c2;
assign c3 = ((a[2] ^ b[2])& c2) | (a[2] & b[2]);
assign s3 = a[3] ^ b[3] ^ c3;
assign c4= ((a[3] ^ b[3])& c3) | (a[3] & b[3]);
assign s4 = a[4] ^ b[4] ^ c4;
assign c5= ((a[4] ^ b[4])& c4) | (a[4]& b[4]);
assign s5 = a[5] ^ b[5] ^ c5;
assign c6 = ((a[5] ^ b[5])& c5) | (a[5] & b[5]) ;
assign s6 = a[6] ^ b[6] ^ c6;
assign c7 = ((a[6] ^ b[6])& c6) | (a[6] & b[6]);
assign s7 = a[7] ^ b[7] ^ c7;
assign carry = ((a[7] ^ b[7])& c7) | (a[7] & b[7]) ;
assign sum = { carry, s7, s6, s5, s4, s3, s2, s1, s0};
endmodule
module add8(
input [7:0] a,
input [7:0] b,
output [8:0] sum
);
wire s0;
wire c1;
wire s1;
wire c2;
wire s2;
wire c3;
wire s3;
wire c4;
wire s4;
wire c5;
wire s5;
wire c6;
wire s6;
wire s7;
wire c7;
wire carry;
assign s0 = a[0] ^ b[0];
assign c1 = ((a[0] ^ b[0]) & 1'b0 )| (a[0] & b[0]); // for select line and ? for condition statement
assign s1 = a[1] ^ b[1] ^ c1;
assign c2 = ((a[1] ^ b[1]) & c1) | (a[1] & b[1]);
assign s2 = a[2] ^ b[2] ^ c2;
assign c3 = ((a[2] ^ b[2])& c2) | (a[2] & b[2]);
assign s3 = a[3] ^ b[3] ^ c3;
assign c4= ((a[3] ^ b[3])& c3) | (a[3] & b[3]);
assign s4 = a[4] ^ b[4] ^ c4;
assign c5= ((a[4] ^ b[4])& c4) | (a[4]& b[4]);
assign s5 = a[5] ^ b[5] ^ c5;
assign c6 = ((a[5] ^ b[5])& c5) | (a[5] & b[5]) ;
assign s6 = a[6] ^ b[6] ^ c6;
assign c7 = ((a[6] ^ b[6])& c6) | (a[6] & b[6]);
assign s7 = a[7] ^ b[7] ^ c7;
assign carry = ((a[7] ^ b[7])& c7) | (a[7] & b[7]) ;
assign sum = { carry, s7, s6, s5, s4, s3, s2, s1, s0};
endmodule
