verilog code need help

[vead]

I have made sample code for 4 bit ALU and 3 to 8 decoder to make 4 bit processor . as designer we can design anything so I have started to design processor with two function ALU and decoder

specification
4 bit processor
4 bit ALU
3 to 8 decoder

4 bit ALU verilog code

Module alu (a,b,s0,s1,s2 f);
Input a,b,s0,s1,s2;
Output f;
Reg [3:0];
Always @(s0,s1,s2);
Begian
Case (s0,s1,s2);
3b’000 :f=(a&b);
3b’001:f= (a|b);
3b’010 :f= ~(a&b);
3b’011 :f= ~ (a|b);
3b’100:f=(a^b);
3b’101: f=(a*b);
3b’110: f=(a+b);
3b’111:f=(a-b );
End case
End module

3 to 8 decoder

Module decoder (a2,a1,a0, d7,d6,d5,d4,d3,d2,d1,d0);
Input a2,a1,a0;
Output d7,d6,d5,d4,d3,d2,d1,d0;
Wire [7:0];
Always @(a2,a1,a0);
Begin
Case (a2,a1,a0);
4’b000:( d7,d6,d5,d4,d3,d2,d1,d0)=00000001;
4’001: (d7,d6,d5,d4,d3,d2,d1,d0)=00000010;
4’b010: (d7,d6,d5,d4,d3,d2,d1,d0)=00000100;
4’b011: (d7,d6,d5,d4,d3,d2,d1,d0)=00001000;
4’b100:( d7,d6,d5,d4,d3,d2,d1,d0)=00010000;
4’b101:( d7,d6,d5,d4,d3,d2,d1,d0)=00100000;
4’b110: (d7,d6,d5,d4,d3,d2,d1,d0)=01000000;
4’b111: (d7,d6,d5,d4,d3,d2,d1,d0)=10000000;
Endcase
Endmodule

I don't understand how to connect 4 bit Alu with
3 to 8 bit decoder to make 4 bit processor

 

[(*steve*)]

Which of these units performs the fetch/execute cycle, and where is the program counter stored? Do you have any registers? What memory addressing modes do you have?

At the moment you're question sounds like "I have a steering wheel and a belt buckle. How do I join them to make a car?"

 

[vead]

Which of these units performs the fetch/execute cycle, and where is the program counter stored? Do you have any registers? What memory addressing modes do you have?

At the moment you're question sounds like "I have a steering wheel and a belt buckle. How do I join them to make a car?"

ALU perform following function

AND logic
OR logic
NAND logic
NOR logic
X or logic
X nor logic
addition
subtraction

I am not going to design for specific purpose
don't mind I made some simple specification for 4 bit processor
specification for 4 bit processor

1)4 bit ALU
2)3:8 decoder
3) 4 bit A register ( data register )
4) 4 bit B register (data register )
5) 4 bit Instruction register
6)4 bit address register
look at this thread https://www.electronicspoint.com/threads/n-bit-alu.270176/#post-1621647

 

[(*steve*)]

I think the problem is that you have no idea what is actually required.

Do you, for example, know what the fetch-execute cycle is?

Do you understand how many addresses you can have with a 4 bit address register?

Do you understand that the data bus and the address bus can be (and often are) different widths?

 

[vead]

I think the problem is that you have no idea what is actually required.

ok my effort for design

4 bit processor
1)4 bit ALU
2)3:8 decoder
3) 4 bit A register ( data register )
4) 4 bit B register (data register )
5) 4 bit Instruction register
6)4 bit address register
7)8 bit counter
8)4 bit data bus
9)4 bit address bus
10)4 bit control bus

Do you, for example, know what the fetch-execute cycle is?

Instruction is fetch and execute

Do you understand how many addresses you can have with a 4 bit address register

16 address

Do you understand that the data bus and the address bus can be (and often are) different widths

I don't know reason
I will research
we write verilog code for Alu , decoder counter , register,.........etc
but how we write code for processor I am not asking for all code I want to ask how we connect alu decoder , counter registers and other

 

[(*steve*)]

Instruction is fetch and execute

You need to look this up and see what it actually means.

I also can't particularly see why you need a 3:8 decoder to do what you want.

Before you even think about this you would need to consider your instruction format and determine how this would be encoded in each instruction.

for example, if you have a 4 bit instruction, and you only have 1 bit after the three for your possible ALU actions, then by necessity, the actions would need to be between two fixed registers. This suggests that a single instruction would need to be longer than 4 bits, or that you have simpler ALU commands (perhaps 4 of them, and, or, add, and invert.

This means that when you fetch an instruction, you can decode what is supposed to happen, and send (perhaps) two of those bits to the ALU to determine the action to be performed during the execute part of the cycle.

If you have a 4 bit instruction, the commands might be:

• 000x - load immediate (next word) into register x (0 or 1 -- i.e. you have 2 register)
• 001x - load register x from location specified in the next word
• 010x - save register x to location specified in the next word
• 011x - jump to the location in the next word if register x is zero (alternatively this might only operate on a single register (say register 0)) and 0111 might be an unconditional jump
• 1yyx - perform the ALU function yy (i.e. o to 4) on the registers, placing the result into register x. Alternatively, perhaps you have 1yyy where there are 8 functions and the result always goes into register 0

So now you have an instruction set, you can start to consider how that will be implemented.

Note that the fetch portion of the cycle may need to get one or two words (and consequently increment the program counter by 1 or 2), and then the execute phase may need to address memory, change the program counter, do some ALU operation, or some combination of these.

Now, with 16 memory addresses, you might be able to write a program which reads the values of two memory locations and adds them together before storing the result somewhere, and then stopping by looping.

But it will accomplish something.

But you need to have a plan. As yet I can't see that you have the understanding required to make one. If you wish, you can take this one. If you can implement this then you might want to build on it.

Perhaps you might think of whether you want to use a Harvard or a Von Neumann architecture as well.

 

[vead]

Before you even think about this you would need to consider your instruction format and determine how this would be encoded in each instruction.

Instruction format

0 0 0 do AND logic

000 xxx
AND XXX

0 0 1 do OR logic
001xxx
ORxxx

0 1 0 do Nand logic
010xxx
NANDxxx
0 1 1 do nor logic
011xxx
norxxx

1 0 0 do Xor logic
100xxx
norxxx

1 0 1 do X nor
101xxx
Xorxxx

1 1 0 do addition
110xxx
Addxxx

1 1 1 do subtraction
111xxx
subxxx


tables
0 0 0 AND logic

0 1 0

1 0 0

1 1 1

0 0 0 Or logic

0 1 1

1 0 1

1 1 1


0 0 1 NAND

0 1 1

1 0 1

1 1 0

0 0 1 NOR

0 1 0

1 0 0

1 1 0


0 0 0 Xor

0 1 1

1 0 1

1 1 0

0 0 1 Xnor

0 1 0

1 0 0

1 1 1


0 0 0 addition

0 1 1

1 0 1

1 1 0

0 0 0 subtraction

0 1 1

1 0 1

1 1 0

I will write verilog code for counter, registers and others but how to connect alu and decoder