VERILOG and VHDL

[martin griffith]

The Xilinx schematic library also has a lot of 74xx TTL blocks, plus a
lot of general-purpose latches and counters and gates and stuff.

You can grossly waste resources here, like using three outputs of a
1:16 decoder, or five bits of an 8-bit latch; the compiler will strip
out the stuff that's not actively used.

John

Thanks John (and Slurp, nice nik)

I've got to drag myself into this century, before nanotech makes us
all obsolete.

What is it with these high tech sites that making buying some sexy
underware for the (ex) missus is simpler than choosing a product for
design?



martin

 

[Joel Kolstad]

Of course. Not everybody can produce high-speed, complex, bug-free
designs.

Cute, John, but there are plenty of people out there who can both produce
high-speed, complex, bug-free designs and use HDLs.

In fact, I'd suggest that whether or not any given individual can produce
those designs has a lot more to do with the person than the tools they're
using. Although there are occasions where tools can be blamed for producing
crap results, I think many people are far too quick to blame their tools for
something not working when it's really their own skill set that's lacking.
Indeed, one of the claims of EDA tool marketing seems to be something very
close to, "...letting your unskilled employees produce results that formerly
required someone with skills!" It's not a claim completely without merit...
you and I might winge to see someone writing an LED flasher in C using a
100,000 gate microcontroller rather than a couple of transistors, but at the
end of the day the economy only cares about (1) is the problem solved in a
*more or less* bug-free way and (2) what's the price?

---Joel

 

[Rich Grise]

The Xilinx schematic library also has a lot of 74xx TTL blocks, plus a
lot of general-purpose latches and counters and gates and stuff.

You can grossly waste resources here, like using three outputs of a
1:16 decoder, or five bits of an 8-bit latch; the compiler will strip
out the stuff that's not actively used.

And don't be afraid to browse the device library ( or whatever it's called) -
I spend a couple days tediously making a multiplier out of adders and
data selectors, only to discover that "multiplier" is one of the
primitives. Also, "RAM", much to my surprise.

One of these days, I'm gonna flash an LED! ;-)

Cheers!
Rich

 

[Rich Grise]

What is it with these high tech sites that making buying some sexy
underware for the (ex) missus is simpler than choosing a product for
design?

System Requirements. ;-)

And it's pretty well known that just about the only web business that
makes any money at all is porn. ;-)

Cheers!
Rich

 

[John Larkin]

And don't be afraid to browse the device library ( or whatever it's called) -
I spend a couple days tediously making a multiplier out of adders and
data selectors, only to discover that "multiplier" is one of the
primitives. Also, "RAM", much to my surprise.

With a few clicks, you can generate a pipelined 13x18
signed-x-unsigned saturating multiplier, or a numerical-controlled
oscillator, or a dual-port synchronous RAM or, well, all sorts of
stuff. One of our current designs includes eight saturating
fixed-point dividers, just because the FPGA can do it faster than the
uP.

John

 

[[email protected]]

What we can say about this never end debate?
I began my long FPGA exploration with schematics, all in schematics
nothing else. One day, I figured out that I need to know VHDL to read
what other FPGA guys thinking,...
IMO both have advantage/disadvantage to the other.

Schematics the good
* Suitable for small design /stable products
* Quick
* Easy to review & understand
* Less hiden bug risk
* Easy to go to lowest RTL level, WYSIWYG (if the tool has no bug

Schematics the bad
* Not suitable for big complex design
* Difficulties for major upgrade/modification, remember your 1st grade
drawing skill?
* Hard copy & documentation

Schematic the ugly
* It looks ugly under the some hands, I mean it really ugly!
* Not easy to migrate to other tools/devices
* Take long design time for big & complex. Remember your first
schematic statemachine?

VHDL ? I would like to let others bring up the points

cheers,

 

[Joel Kolstad]

Schematics the good
* Suitable for small design /stable products
Sure

* Quick
OK

* Easy to review & understand

Maybe -- it's just as easy to make a difficult-to-comprehend schematic as it
is an HDL file.

* Less hiden bug risk

Maybe -- some tools convert schematics to HDLs prior to synthesis, in which
case there's arguably MORE chances for "hidden bugs" to creep in.

* Easy to go to lowest RTL level, WYSIWYG (if the tool has no bug

Another "maybe:" trying dropping down a schematic symbol for a multiplier and
compare the results to just using a multiply command in an HDL -- the bulk of
the result will be identical.

Schematics the bad
* Not suitable for big complex design

I wouldn't debate this personally, but playing devil's advocate: I'd say it
just takes *more effort* to do a "big, complex" design in schematics. They
were certainly done back before HDLs were available, after all.

* Difficulties for major upgrade/modification, remember your 1st grade
drawing skill?

It's not really "difficult," it's more just "slower" -- you have to re-draw a
lot.

* Hard copy & documentation

Possibly... if you archive everything as PDF it should be OK.

Schematic the ugly
* It looks ugly under the some hands, I mean it really ugly!

True, but as mentioned above, some people write really ugly HDL too.

* Not easy to migrate to other tools/devices

Here again I'd say "mainly slower" -- if you migrate from, e.g., Xilinx to
Altera, there's going to be a fair amount of design re-entry done (for a
complex design) regardless of the choice of HDL vs. schem.

* Take long design time for big & complex. Remember your first
schematic statemachine?

Yes, although for truly "big and complex" designs, the design entry time
should be small relative to the design, uh, design time itself. Of course,
I'd still prefer the shortest design entry time.

VHDL ? I would like to let others bring up the points

As I mentioned before, all contemporary tools support "mixed mode" design
entry, so you might as well let your engineers use whatever they're most
comfortable with so long as the results are well-organized and thus accessible
to others.

---Joel Kolstad

 

[Rich Grise]

What we can say about this never end debate?

For one, don't top-post. It interrupts the natural flow of the thread.

I began my long FPGA exploration with schematics, all in schematics
nothing else. One day, I figured out that I need to know VHDL to read
what other FPGA guys thinking,...
IMO both have advantage/disadvantage to the other.

Schematics the good

Schematics the bad

Schematic the ugly

VHDL ? I would like to let others bring up the points

The Xilinx Web-pack, downloadable for free (although you'll need some
kind of hardware to actually do anything), lets you use any of the three
at any time, AFAIK. I'm still doing the tutorials, admittedly
sporadically, but so far it's fascinating. It seems that VHDL and Verilog
do almost exactly the same thing, except the window-dressing of one
reminds me of the window-dressing of Pascal, and the other reminds me of
C, but I can never remember which.

And you can mix in schematics into the same design.

So, my bottom line, I don't know why I should choose VHDL or Verilog over
the other - So far, I've just been doing what the tutorials say, and they
seem to be working so far.

Cheers!
Rich

 

[Rich Grise]

I wouldn't debate this personally, but playing devil's advocate: I'd say it
just takes *more effort* to do a "big, complex" design in schematics. They
were certainly done back before HDLs were available, after all.

I saw a write-up once of the Motorola 6809 development team, and there was
one snapshot of three or four guys standing, admiring this schematic on
the wall that was about 12' (4m) wide and about 9' (3m) tall.

It was the whole microprocessor. I almost had a geek out-of-body
experience. ;-)

Mostly what I've done has been pretty much connect-the-dots. When I was a
video game repairman, I had the opportunity to look at the schematic of
Pac-Man (hell, "look" at the schamatic? I _fixed_ the boards!) and the
sound generator was just a state machine. A PROM and a latch, and one of
the output bits went to the speaker driver. That made me drool. I wonder
what the "program" looked like?

Cheers!
Rich

 

[Paul Burke]

VHDL ? I would like to let others bring up the points

VHDL? So good you've got to say everything twice.

 

[amar]

vhdl written by douglas l.perry is one of the best book for vhdl langwg

 

[amar]

VHDL WRITTEN BY DOUGLAS L.PERRY is aan best book